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URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

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  • This comparison shows the changes necessary to convert path 
    /hf-risc/trunk/hf-riscv/platform/spartan3_starterkit
    from Rev 15 to Rev 18
    ↔ Reverse comparison
  •

Rev 15 → Rev 18

/spartan3.vhd
2,7 → 2,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hellfire_cpu_if is
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
14,11 → 14,11
uart_read: in std_logic;
uart_write: out std_logic
);
end hellfire_cpu_if;
end hfrisc_soc;
 
architecture interface of hellfire_cpu_if is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
begin
64,19 → 64,16
data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
 
-- HF-RISCV core
-- HF-RISC core
core: entity work.datapath
port map( clock => clock,
reset => reset,
stall => stall_cpu,
busy => busy_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
95,14 → 92,11
stall => stall,
 
stall_cpu => stall_cpu,
busy_cpu => busy_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
187,5 → 181,5
data_o => data_read_ram(31 downto 24)
);
 
end interface;
end top_level;
 
/spartan3_SRAM.ucf
8,6 → 8,24
NET "uart_write" LOC = "R13"; #RX
NET "uart_read" LOC = "T13"; #TX
 
NET "extio_in<0>" LOC = "C5";
NET "extio_in<1>" LOC = "C6";
NET "extio_in<2>" LOC = "C7";
NET "extio_in<3>" LOC = "C8";
NET "extio_in<4>" LOC = "C9";
NET "extio_in<5>" LOC = "A3";
NET "extio_in<6>" LOC = "A4";
NET "extio_in<7>" LOC = "A5";
 
NET "extio_out<0>" LOC = "D5";
NET "extio_out<1>" LOC = "D6";
NET "extio_out<2>" LOC = "E7";
NET "extio_out<3>" LOC = "D7";
NET "extio_out<4>" LOC = "D8";
NET "extio_out<5>" LOC = "D10";
NET "extio_out<6>" LOC = "B4";
NET "extio_out<7>" LOC = "B5";
 
NET "ram_address<2>" LOC = "L5";
NET "ram_address<3>" LOC = "N3";
NET "ram_address<4>" LOC = "M4";
/spartan3_SRAM.vhd
2,7 → 2,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hellfire_cpu_if is
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
14,6 → 14,9
uart_read: in std_logic;
uart_write: out std_logic;
 
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0);
 
ram_address: out std_logic_vector(31 downto 2);
ram_data: inout std_logic_vector(31 downto 0);
ram_ce1_n: out std_logic;
25,12 → 28,11
ram_we_n: out std_logic;
ram_oe_n: out std_logic
);
end hellfire_cpu_if;
end hfrisc_soc;
 
architecture interface of hellfire_cpu_if is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_we, data_w_cpu: std_logic_vector(3 downto 0);
 
signal we_n_next : std_logic;
38,7 → 40,7
signal data_reg : std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
process (reset_in, clk_in, clock, we_n_next)
begin
if reset_in = '1' then
clock <= '0';
47,6 → 49,18
clock <= not clock;
end if;
end if;
 
if reset_in = '1' then
we_n_reg <= '1';
elsif rising_edge(clk_in) then
we_n_reg <= we_n_next or not clock;
end if;
 
if reset_in = '1' then
data_read_ram <= (others => '0');
elsif rising_edge(clock) then
data_read_ram <= ram_data;
end if;
end process;
 
-- reset synchronizer
61,16 → 75,13
end if;
end process;
 
process (reset, clock, ext_irq, ram_enable_n, ram_data)
 
process (reset, clock, ram_enable_n)
begin
if reset = '1' then
data_read_ram <= (others => '0');
ram_dly <= '0';
ext_irq <= x"00";
elsif clock'event and clock = '1' then
data_read_ram <= ram_data;
ram_dly <= not ram_enable_n;
ext_irq <= "0000000" & int_in;
end if;
end process;
 
78,19 → 89,16
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
 
-- HF-RISCV core
-- HF-RISC core
core: entity work.datapath
port map( clock => clock,
reset => reset,
stall => stall_cpu,
busy => busy_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
109,14 → 117,11
stall => stall,
 
stall_cpu => stall_cpu,
busy_cpu => busy_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
126,8 → 131,8
data_read_mem => data_read,
data_write_mem => data_write,
data_we_mem => data_we,
extio_in => ext_irq,
extio_out => open,
extio_in => extio_in,
extio_out => extio_out,
uart_read => uart_read,
uart_write => uart_write
);
151,6 → 156,7
-- the address bus is controlled directly by the CPU.
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
ram_address <= address(31 downto 2);
ram_we_n <= we_n_reg;
 
ram_control:
process(clock, ram_enable_n, data_we, data_write)
164,19 → 170,19
ram_lb1_n <= '0';
ram_ub2_n <= '0';
ram_lb2_n <= '0';
ram_we_n <= '1';
we_n_next <= '1';
ram_oe_n <= '0';
else -- write
ram_data <= data_write;
if clock = '1' then
ram_data <= (others => 'Z');
else
ram_data <= data_write;
end if;
ram_ub1_n <= not data_we(3);
ram_lb1_n <= not data_we(2);
ram_ub2_n <= not data_we(1);
ram_lb2_n <= not data_we(0);
if clock = '0' then
ram_we_n <= '0';
else
ram_we_n <= '1';
end if;
we_n_next <= '0';
ram_oe_n <= '1';
end if;
else
187,10 → 193,10
ram_ce2_n <= '1';
ram_ub2_n <= '1';
ram_lb2_n <= '1';
ram_we_n <= '1';
we_n_next <= '1';
ram_oe_n <= '1';
end if;
end process;
 
end interface;
end top_level;
 

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