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https://opencores.org/ocsvn/hf-risc/hf-risc/trunk
Subversion Repositories hf-risc
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- This comparison shows the changes necessary to convert path
/hf-risc/trunk
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/ucore/peripherals_busmux.vhd
9,9 → 9,9
-- FETCH: instruction memory is accessed (address is PC), data becomes available in one cycle. PC is updated. |
-- DECODE: an instruction is fed into the decoding / control logic and values are registered for the next |
-- stage. pipeline stalls, as well as bubble insertion is performed in this stage. |
-- EXECUTE: the register file is accessed and the ALU calculates the result. data address is put on the bus |
-- and data is put on data out bus (stores) or data is copied to the register file (loads) or simply the |
-- result (or pc) is written to the register file (normal operations). branches are calculated. |
-- EXECUTE: the register file is accessed and the ALU calculates the result. data access is performed (loads |
-- and stores) or simply the result (or pc) is written to the register file (normal operations). branch target |
-- and outcome are calculated. |
-- |
-- *This design is a compromise between performance, area and complexity. |
-- *Only the absolutely *needed* MIPS-I opcodes are implemented. This core was implemented with the C programming |