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Subversion Repositories hf-risc

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  • This comparison shows the changes necessary to convert path 
    /hf-risc
    from Rev 18 to Rev 19
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  •

Rev 18 → Rev 19

/trunk/hf-risc/ucore/peripherals_busmux.vhd
90,22 → 90,30
--
-- Interrupt masks:
--
-- IRQ_COUNTER 0x0001 (bit 18 of the counter is set)
-- IRQ_COUNTER_NOT 0x0002 (bit 18 of the counter is clear)
-- IRQ_COUNTER2 0x0004 (bit 16 of the counter is set)
-- IRQ_COUNTER2_NOT 0x0008 (bit 16 of the counter is clear)
-- IRQ_COMPARE 0x0010 (counter is equal to compare, clears irq when updated)
-- IRQ_COMPARE2 0x0020 (counter bits 23 to 0 are equal to compare2, clears irq when updated)
-- IRQ_UART_READ_AVAILABLE 0x0040 (there is data available for reading on the UART)
-- IRQ_UART_WRITE_AVAILABLE 0x0080 (UART is not busy)
-- EXT_IRQ0 0x0100 (external interrupts on extio_in, 'high' level triggered)
-- EXT_IRQ1 0x0200
-- EXT_IRQ2 0x0400
-- EXT_IRQ3 0x0800
-- EXT_IRQ4 0x1000
-- EXT_IRQ5 0x2000
-- EXT_IRQ6 0x4000
-- EXT_IRQ7 0x8000
-- IRQ_COUNTER 0x00000001 (bit 18 of the counter is set)
-- IRQ_COUNTER_NOT 0x00000002 (bit 18 of the counter is clear)
-- IRQ_COUNTER2 0x00000004 (bit 16 of the counter is set)
-- IRQ_COUNTER2_NOT 0x00000008 (bit 16 of the counter is clear)
-- IRQ_COMPARE 0x00000010 (counter is equal to compare, clears irq when updated)
-- IRQ_COMPARE2 0x00000020 (counter bits 23 to 0 are equal to compare2, clears irq when updated)
-- IRQ_UART_READ_AVAILABLE 0x00000040 (there is data available for reading on the UART)
-- IRQ_UART_WRITE_AVAILABLE 0x00000080 (UART is not busy)
-- EXT_IRQ0 0x00010000 (external interrupts on extio_in, high level triggered)
-- EXT_IRQ1 0x00020000
-- EXT_IRQ2 0x00040000
-- EXT_IRQ3 0x00080000
-- EXT_IRQ4 0x00100000
-- EXT_IRQ5 0x00200000
-- EXT_IRQ6 0x00400000
-- EXT_IRQ7 0x00800000
-- EXT_IRQ0_NOT 0x01000000 (external interrupts on extio_in, low level triggered)
-- EXT_IRQ1_NOT 0x02000000
-- EXT_IRQ2_NOT 0x04000000
-- EXT_IRQ3_NOT 0x08000000
-- EXT_IRQ4_NOT 0x10000000
-- EXT_IRQ5_NOT 0x20000000
-- EXT_IRQ6_NOT 0x40000000
-- EXT_IRQ7_NOT 0x80000000
 
library ieee;
use ieee.std_logic_1164.all;
146,9 → 154,9
 
architecture arch of busmux is
signal write_enable: std_logic;
signal irq_cause, irq_mask_reg, uart_divisor: std_logic_vector(15 downto 0);
signal uart_divisor: std_logic_vector(15 downto 0);
signal irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
signal periph_data, irq_vector_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
signal periph_data, irq_vector_reg, irq_cause, irq_mask_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
signal compare2_reg: std_logic_vector(23 downto 0);
signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
173,9 → 181,9
when "0000" => -- IRQ_VECTOR (RW)
periph_data <= irq_vector_reg;
when "0001" => -- IRQ_CAUSE (RO)
periph_data <= x"0000" & irq_cause;
periph_data <= irq_cause;
when "0010" => -- IRQ_MASK (RW)
periph_data <= x"0000" & irq_mask_reg;
periph_data <= irq_mask_reg;
when "0011" => -- IRQ_STATUS (RW)
periph_data <= x"000000" & irq_status_reg;
when "0100" => -- IRQ_EPC (RO)
207,16 → 215,16
process(clock, reset, counter_reg, address_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
begin
if reset = '1' then
irq_vector_reg <= x"00000000";
irq_mask_reg <= x"0000";
irq_status_reg <= x"00";
counter_reg <= x"00000000";
compare_reg <= x"00000000";
irq_vector_reg <= (others => '0');
irq_mask_reg <= (others => '0');
irq_status_reg <= (others => '0');
counter_reg <= (others => '0');
compare_reg <= (others => '0');
compare_trig <= '0';
compare2_reg <= x"000000";
compare2_reg <= (others => '0');
compare2_trig <= '0';
extio_out_reg <= x"00";
uart_divisor <= x"0000";
extio_out_reg <= (others => '0');
uart_divisor <= (others => '0');
elsif clock'event and clock = '1' then
counter_reg <= counter_reg + 1;
if compare_reg = counter_reg then
230,7 → 238,7
when "0000" => -- IRQ_VECTOR
irq_vector_reg <= data_out_cpu;
when "0010" => -- IRQ_MASK
irq_mask_reg <= data_out_cpu(15 downto 0);
irq_mask_reg <= data_out_cpu;
when "0011" => -- IRQ_STATUS
irq_status_reg <= data_out_cpu(7 downto 0);
when "0110" => -- IRQ_COMPARE
325,7 → 333,7
 
-- interrupts and peripherals
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
irq_cause <= extio_in & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
irq_cause <= not extio_in & extio_in & x"00" & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
 
irq_cpu <= irq;
irq_vector_cpu <= irq_vector_reg;
/trunk/hf-riscv/core_rv32i/peripherals_busmux.vhd
66,22 → 66,30
--
-- Interrupt masks:
--
-- IRQ_COUNTER 0x0001 (bit 18 of the counter is set)
-- IRQ_COUNTER_NOT 0x0002 (bit 18 of the counter is clear)
-- IRQ_COUNTER2 0x0004 (bit 16 of the counter is set)
-- IRQ_COUNTER2_NOT 0x0008 (bit 16 of the counter is clear)
-- IRQ_COMPARE 0x0010 (counter is equal to compare, clears irq when updated)
-- IRQ_COMPARE2 0x0020 (counter bits 23 to 0 are equal to compare2, clears irq when updated)
-- IRQ_UART_READ_AVAILABLE 0x0040 (there is data available for reading on the UART)
-- IRQ_UART_WRITE_AVAILABLE 0x0080 (UART is not busy)
-- EXT_IRQ0 0x0100 (external interrupts on extio_in, 'high' level triggered)
-- EXT_IRQ1 0x0200
-- EXT_IRQ2 0x0400
-- EXT_IRQ3 0x0800
-- EXT_IRQ4 0x1000
-- EXT_IRQ5 0x2000
-- EXT_IRQ6 0x4000
-- EXT_IRQ7 0x8000
-- IRQ_COUNTER 0x00000001 (bit 18 of the counter is set)
-- IRQ_COUNTER_NOT 0x00000002 (bit 18 of the counter is clear)
-- IRQ_COUNTER2 0x00000004 (bit 16 of the counter is set)
-- IRQ_COUNTER2_NOT 0x00000008 (bit 16 of the counter is clear)
-- IRQ_COMPARE 0x00000010 (counter is equal to compare, clears irq when updated)
-- IRQ_COMPARE2 0x00000020 (counter bits 23 to 0 are equal to compare2, clears irq when updated)
-- IRQ_UART_READ_AVAILABLE 0x00000040 (there is data available for reading on the UART)
-- IRQ_UART_WRITE_AVAILABLE 0x00000080 (UART is not busy)
-- EXT_IRQ0 0x00010000 (external interrupts on extio_in, high level triggered)
-- EXT_IRQ1 0x00020000
-- EXT_IRQ2 0x00040000
-- EXT_IRQ3 0x00080000
-- EXT_IRQ4 0x00100000
-- EXT_IRQ5 0x00200000
-- EXT_IRQ6 0x00400000
-- EXT_IRQ7 0x00800000
-- EXT_IRQ0_NOT 0x01000000 (external interrupts on extio_in, low level triggered)
-- EXT_IRQ1_NOT 0x02000000
-- EXT_IRQ2_NOT 0x04000000
-- EXT_IRQ3_NOT 0x08000000
-- EXT_IRQ4_NOT 0x10000000
-- EXT_IRQ5_NOT 0x20000000
-- EXT_IRQ6_NOT 0x40000000
-- EXT_IRQ7_NOT 0x80000000
 
library ieee;
use ieee.std_logic_1164.all;
123,9 → 131,9
 
architecture arch of busmux is
signal write_enable: std_logic;
signal irq_cause, irq_mask_reg, uart_divisor: std_logic_vector(15 downto 0);
signal uart_divisor: std_logic_vector(15 downto 0);
signal irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
signal periph_data, irq_vector_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
signal periph_data, irq_vector_reg, irq_cause, irq_mask_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
signal compare2_reg: std_logic_vector(23 downto 0);
signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
150,9 → 158,9
when "0000" => -- IRQ_VECTOR (RW)
periph_data <= irq_vector_reg;
when "0001" => -- IRQ_CAUSE (RO)
periph_data <= irq_cause(7 downto 0) & irq_cause(15 downto 8) & x"0000";
periph_data <= irq_cause(7 downto 0) & irq_cause(15 downto 8) & irq_cause(23 downto 16) & irq_cause(31 downto 24);
when "0010" => -- IRQ_MASK (RW)
periph_data <= irq_mask_reg(7 downto 0) & irq_mask_reg(15 downto 8) & x"0000";
periph_data <= irq_mask_reg(7 downto 0) & irq_mask_reg(15 downto 8) & irq_mask_reg(23 downto 16) & irq_mask_reg(31 downto 24);
when "0011" => -- IRQ_STATUS (RW)
periph_data <= irq_status_reg & x"000000";
when "0100" => -- IRQ_EPC (RO)
184,16 → 192,16
process(clock, reset, counter_reg, address_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
begin
if reset = '1' then
irq_vector_reg <= x"00000000";
irq_mask_reg <= x"0000";
irq_status_reg <= x"00";
counter_reg <= x"00000000";
compare_reg <= x"00000000";
irq_vector_reg <= (others => '0');
irq_mask_reg <= (others => '0');
irq_status_reg <= (others => '0');
counter_reg <= (others => '0');
compare_reg <= (others => '0');
compare_trig <= '0';
compare2_reg <= x"000000";
compare2_reg <= (others => '0');
compare2_trig <= '0';
extio_out_reg <= x"00";
uart_divisor <= x"0000";
extio_out_reg <= (others => '0');
uart_divisor <= (others => '0');
elsif clock'event and clock = '1' then
counter_reg <= counter_reg + 1;
if compare_reg = counter_reg then
207,7 → 215,7
when "0000" => -- IRQ_VECTOR
irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
when "0010" => -- IRQ_MASK
irq_mask_reg <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
irq_mask_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
when "0011" => -- IRQ_STATUS
irq_status_reg <= data_out_cpu(31 downto 24);
when "0110" => -- IRQ_COMPARE
302,7 → 310,7
 
-- interrupts and peripherals
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
irq_cause <= extio_in & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
irq_cause <= not extio_in & extio_in & x"00" & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
 
irq_cpu <= irq;
irq_vector_cpu <= irq_vector_reg;

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