OpenCores
URL https://opencores.org/ocsvn/hwlu/hwlu/trunk

Subversion Repositories hwlu

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  • This comparison shows the changes necessary to convert path 
    /hwlu/trunk/rtl/vhdl
    from Rev 4 to Rev 5
    ↔ Reverse comparison
  •

Rev 4 → Rev 5

/csa8.vhd
0,0 → 1,155
----==============================================================----
---- ----
---- Filename: csa8.vhd ----
---- Module description: Top-level module of 8-bit carry-select ----
---- adder ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Add a parameterized version of a fast adder ----
---- (probably a carry select adder). ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
entity add is
generic (
DW : integer := 8
);
port (
a : in std_logic_vector(DW-1 downto 0);
b : in std_logic_vector(DW-1 downto 0);
sum : out std_logic_vector(DW-1 downto 0)
);
end add;
 
architecture structural of add is
-- Component declarations
component fa
port (
a : in std_logic;
b : in std_logic;
ci : in std_logic;
s : out std_logic;
co : out std_logic
);
end component;
--
component mux2_1
generic (
DW : integer := 8
);
port (
in0 : in std_logic_vector(DW-1 downto 0);
in1 : in std_logic_vector(DW-1 downto 0);
sel : in std_logic;
mout : out std_logic_vector(DW-1 downto 0)
);
end component;
--
-- Constant declarations
constant zero_1b : std_logic := '0';
constant one_1b : std_logic := '1';
--
-- Signal declarations
signal carry : std_logic_vector(4 downto 0);
signal c_up_ci0 : std_logic_vector(4 downto 0);
signal c_up_ci1 : std_logic_vector(4 downto 0);
signal s_up_ci0 : std_logic_vector(3 downto 0);
signal s_up_ci1 : std_logic_vector(3 downto 0);
--
begin
carry(0) <= '0';
--
U_fa0_3_cells : for i in 0 to 3 generate
U_fa : fa
port map (
a => a(i),
b => b(i),
ci => carry(i),
s => sum(i),
co => carry(i+1)
);
end generate U_fa0_3_cells;
c_up_ci0(0) <= zero_1b;
c_up_ci1(0) <= one_1b;
U_fa4_7_ci0_cells : for i in 0 to 3 generate
U_fa : fa
port map (
a => a(i+4),
b => b(i+4),
ci => c_up_ci0(i),
s => s_up_ci0(i),
co => c_up_ci0(i+1)
);
end generate U_fa4_7_ci0_cells;
 
U_fa4_7_ci1_cells : for i in 0 to 3 generate
U_fa : fa
port map (
a => a(i+4),
b => b(i+4),
ci => c_up_ci1(i),
s => s_up_ci1(i),
co => c_up_ci1(i+1)
);
end generate U_fa4_7_ci1_cells;
U_mux_s_up : mux2_1
generic map (
DW => 4
)
port map (
in0 => s_up_ci0(3 downto 0),
in1 => s_up_ci1(3 downto 0),
sel => carry(4),
mout => sum(7 downto 4)
);
end structural;
/index_inc.vhd
0,0 → 1,131
----==============================================================----
---- ----
---- Filename: index_inc.vhd ----
---- Module description: Index increment-by-one unit ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Probably remains as current ----
---- (to promote as stable version) ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
 
entity index_inc is
generic (
DW : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
inc_en : in std_logic;
index_plus_one : out std_logic_vector(Dw-1 downto 0);
index_out : out std_logic_vector(DW-1 downto 0)
);
end index_inc;
 
architecture rtl of index_inc is
--
-- Component declarations
component add
generic (
DW : integer := 8
);
port (
a : in std_logic_vector(DW-1 downto 0);
b : in std_logic_vector(DW-1 downto 0);
sum : out std_logic_vector(DW-1 downto 0)
);
end component;
--
component reg_dw
generic (
DW : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
load : in std_logic;
d : in std_logic_vector(DW-1 downto 0);
q : out std_logic_vector(DW-1 downto 0)
);
end component;
--
-- Constant declarations
constant one_dw : std_logic_vector(DW-1 downto 0) := conv_std_logic_vector(1,DW);
--
-- Signal declarations
signal index_rin, index_r : std_logic_vector(DW-1 downto 0);
--
begin
U_adder : add
generic map (
DW => DW
)
port map (
a => index_r,
b => one_dw,
sum => index_rin
);
 
U_reg_dw : reg_dw
generic map (
DW => DW
)
port map (
clk => clk,
reset => reset,
load => inc_en,
d => index_rin,
q => index_r
);
index_out <= index_r;
index_plus_one <= index_rin;
end rtl;
/hw_loops5_top.vhd
0,0 → 1,187
----==============================================================----
---- ----
---- Filename: hw_loops5_top.vhd ----
---- Module description: Top-level file for the hw_looping unit. ----
---- Also implements input and output ----
---- wrapping operations. ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Part of the hwlu OPENCORES project generated automatically ----
---- with the use of the "gen_hw_looping" tool ----
---- ----
---- To Do: ----
---- Considered stable for the time being ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity hw_looping is
generic (
DW : integer := 8;
NLP : integer := 5
);
port (
clk : in std_logic;
reset : in std_logic;
task_loop5_end : in std_logic;
loop1_count : in std_logic_vector(DW-1 downto 0);
loop2_count : in std_logic_vector(DW-1 downto 0);
loop3_count : in std_logic_vector(DW-1 downto 0);
loop4_count : in std_logic_vector(DW-1 downto 0);
loop5_count : in std_logic_vector(DW-1 downto 0);
index1 : out std_logic_vector(DW-1 downto 0);
index2 : out std_logic_vector(DW-1 downto 0);
index3 : out std_logic_vector(DW-1 downto 0);
index4 : out std_logic_vector(DW-1 downto 0);
index5 : out std_logic_vector(DW-1 downto 0);
loops_end : out std_logic
);
end hw_looping;
 
architecture structural of hw_looping is
--
-- Component declarations
component cmpeq
generic (
DW : integer := 8
);
port (
a : in std_logic_vector(DW-1 downto 0);
b : in std_logic_vector(DW-1 downto 0);
reset : in std_logic;
a_eq_b : out std_logic
);
end component;
--
component index_inc
generic (
DW : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
inc_en : in std_logic;
index_plus_one : out std_logic_vector(DW-1 downto 0);
index_out : out std_logic_vector(DW-1 downto 0)
);
end component;
--
component priority_encoder
generic (
NLP : integer := 5
);
port (
flag : in std_logic_vector(NLP-1 downto 0);
task_loop5_end : in std_logic;
incl : out std_logic_vector(NLP-1 downto 0);
reset_vct : out std_logic_vector(NLP-1 downto 0);
loops_end : out std_logic
);
end component;
--
-- Signal declarations
signal flag : std_logic_vector(NLP-1 downto 0);
signal incl : std_logic_vector(NLP-1 downto 0);
signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0);
signal temp_index : std_logic_vector(NLP*DW-1 downto 0);
signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0);
signal reset_vct_penc : std_logic_vector(NLP-1 downto 0);
signal reset_vct_ix : std_logic_vector(NLP-1 downto 0);
--
begin
 
temp_loop_count( ((NLP-0)*DW-1) downto ((NLP-1)*DW) ) <= loop1_count;
temp_loop_count( ((NLP-1)*DW-1) downto ((NLP-2)*DW) ) <= loop2_count;
temp_loop_count( ((NLP-2)*DW-1) downto ((NLP-3)*DW) ) <= loop3_count;
temp_loop_count( ((NLP-3)*DW-1) downto ((NLP-4)*DW) ) <= loop4_count;
temp_loop_count( ((NLP-4)*DW-1) downto ((NLP-5)*DW) ) <= loop5_count;
 
GEN_COMPARATORS: for i in 0 to NLP-1 generate
U_cmp : cmpeq
generic map (
DW => DW
)
port map (
a => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),
b => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ),
reset => reset,
a_eq_b => flag(i)
);
end generate GEN_COMPARATORS;
 
U_priority_enc : priority_encoder
generic map (
NLP => NLP
)
port map (
flag => flag,
task_loop5_end => task_loop5_end,
incl => incl,
reset_vct => reset_vct_penc,
loops_end => loops_end
);
 
GEN_RESET_SEL: for i in 0 to NLP-1 generate
reset_vct_ix(i) <= reset_vct_penc(i) or reset;
end generate GEN_RESET_SEL;
 
GEN_INC_IX: for i in 0 to NLP-1 generate
U_inc_ix1 : index_inc
generic map (
DW => DW
)
port map (
clk => clk,
reset => reset_vct_ix(i),
inc_en => incl(i),
index_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),
index_out => temp_index( ((i+1)*DW-1) downto (i*DW) )
);
end generate GEN_INC_IX;
 
index1 <= temp_index( ((NLP-0)*DW-1) downto ((NLP-1)*DW) );
index2 <= temp_index( ((NLP-1)*DW-1) downto ((NLP-2)*DW) );
index3 <= temp_index( ((NLP-2)*DW-1) downto ((NLP-3)*DW) );
index4 <= temp_index( ((NLP-3)*DW-1) downto ((NLP-4)*DW) );
index5 <= temp_index( ((NLP-4)*DW-1) downto ((NLP-5)*DW) );
 
end structural;
/add_dw.vhd
0,0 → 1,78
----==============================================================----
---- ----
---- Filename: add_dw.vhd ----
---- Module description: Generic DW-bit binary adder ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Probably remains as current ----
---- (to promote as stable version) ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity add is
generic (
DW : integer := 8
);
port (
a : in std_logic_vector(DW-1 downto 0);
b : in std_logic_vector(DW-1 downto 0);
sum : out std_logic_vector(DW-1 downto 0)
);
end add;
architecture structural of add is
signal temp_sum : std_logic_vector(DW downto 0);
begin
--
temp_sum <= (a(DW-1) & a) + (b(DW-1) & b);
sum <= temp_sum(DW-1 downto 0);
--
end structural;
 
 
/cmpeq.vhd
0,0 → 1,73
----==============================================================----
---- ----
---- Filename: cmpeq.vhd ----
---- Module description: Equality comparator ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Probably remains as current ----
---- (to promote as stable version) ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity cmpeq is
generic (
DW : integer := 8
);
port (
a : in std_logic_vector(DW-1 downto 0);
b : in std_logic_vector(DW-1 downto 0);
reset : in std_logic;
a_eq_b : out std_logic
);
end cmpeq;
 
architecture rtl of cmpeq is
begin
--
a_eq_b <= '1' when (a = b and reset = '0') else '0';
--
end rtl;
/fa.vhd
0,0 → 1,73
----==============================================================----
---- ----
---- Filename: fa.vhd ----
---- Module description: Full-adder module ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Probably remains as current ----
---- (to promote as stable version) ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity fa is
port (
a : in std_logic;
b : in std_logic;
ci : in std_logic;
s : out std_logic;
co : out std_logic
);
end fa;
 
 
architecture structural of fa is
begin
--
s <= a xor b xor ci;
co <= ((a xor b) and ci) or (a and b);
--
end structural;
/reg_dw.vhd
0,0 → 1,85
----==============================================================----
---- ----
---- Filename: reg_dw.vhd ----
---- Module description: DW-bit D-type register with synchronous ----
---- reset and load enable ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Probably remains as current ----
---- (to promote as stable version) ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity reg_dw is
generic (
DW : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
load : in std_logic;
d : in std_logic_vector(DW-1 downto 0);
q : out std_logic_vector(DW-1 downto 0)
);
end reg_dw;
architecture rtl of reg_dw is
begin
process (clk, reset, load, d)
begin
if (clk'event and clk = '1') then
-- synchronous reset
if (reset = '1') then
q <= (others => '0');
elsif (load = '1') then
q <= d;
end if; -- reset, load
end if; -- clk
end process;
--
end rtl;
/prenc_loops5.vhd
0,0 → 1,124
----==============================================================----
---- ----
---- Filename: prenc_loops5.vhd ----
---- Module description: Priority encoder unit. Obtains ----
---- increment and reset decisions for the loop indices. ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Part of the hwlu OPENCORES project generated automatically ----
---- with the use of the "gen_priority_encoder" tool ----
---- ----
---- To Do: ----
---- Considered stable for the time being ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity priority_encoder is
generic (
NLP : integer := 5
);
port (
flag : in std_logic_vector(NLP-1 downto 0);
task_loop5_end : in std_logic;
incl : out std_logic_vector(NLP-1 downto 0);
reset_vct : out std_logic_vector(NLP-1 downto 0);
loops_end : out std_logic
);
end priority_encoder;
 
architecture rtl of priority_encoder is
begin
 
-- Fully-nested loop structure with 5 loops
-- From outer to inner: 4-> 3-> 2-> 1-> 0
process (flag, task_loop5_end)
begin
--
-- if loop4 is terminating:
-- reset loops 4-0 to initial index
if (flag(4 downto 0) = "11111") then
incl <= "00000";
reset_vct <= "11111";
loops_end <= '1';
-- else if loop3 is terminating:
-- 1. increment loop4 index
-- 2. reset loop3 to initial index
elsif (flag(3 downto 0) = "1111") then
incl <= "10000";
reset_vct <= "01111";
loops_end <= '0';
-- else if loop2 is terminating:
-- 1. increment loop3 index
-- 2. reset loop2 to initial index
elsif (flag(2 downto 0) = "111") then
incl <= "01000";
reset_vct <= "00111";
loops_end <= '0';
-- else if loop1 is terminating:
-- 1. increment loop2 index
-- 2. reset loop1 to initial index
elsif (flag(1 downto 0) = "11") then
incl <= "00100";
reset_vct <= "00011";
loops_end <= '0';
-- else if loop0 is terminating:
-- 1. increment loop1 index
-- 2. reset loop0 to initial index
elsif (flag(0 downto 0) = "1") then
incl <= "00010";
reset_vct <= "00001";
loops_end <= '0';
-- else increment loop-1 index
else
reset_vct <= "00000";
loops_end <= '0';
if (task_loop5_end = '1') then
incl <= "00001";
else
incl <= "00000";
end if;
end if;
end process;
 
end rtl;
/mux2_1.vhd
0,0 → 1,79
----==============================================================----
---- ----
---- Filename: mux2_1.vhd ----
---- Module description: 2-to-1 DW-bit multiplexer ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
---- ----
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
---- ----
---- To Do: ----
---- Probably remains as current ----
---- (to promote as stable version) ----
---- ----
---- Author: Nikolaos Kavvadias ----
---- nkavv@skiathos.physics.auth.gr ----
---- ----
----==============================================================----
---- ----
---- Copyright (C) 2004 Nikolaos Kavvadias ----
---- nick-kavi.8m.com ----
---- nkavv@skiathos.physics.auth.gr ----
---- nick_ka_vi@hotmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from <http://www.opencores.org/lgpl.shtml> ----
---- ----
----==============================================================----
--
-- CVS Revision History
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity mux2_1 is
generic (
DW : integer := 8
);
port (
in0 : in std_logic_vector(DW-1 downto 0);
in1 : in std_logic_vector(DW-1 downto 0);
sel : in std_logic;
mout : out std_logic_vector(DW-1 downto 0)
);
end mux2_1;
 
 
architecture rtl of mux2_1 is
begin
process (sel, in0, in1)
begin
case sel is
when '0' => mout <= in0;
when others => mout <= in1;
end case;
end process;
--
end rtl;

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