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Rev 44 → Rev 68

/verilog/i2c_slave_model.v
0,0 → 1,341
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant synthesizable I2C Slave model ////
//// ////
//// ////
//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
//// John Sheahan (jrsheahan@optushome.com.au) ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001,2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: i2c_slave_model.v,v 1.4 2003-09-11 08:25:37 rherveille Exp $
//
// $Date: 2003-09-11 08:25:37 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/30 18:11:06 rherveille
// Added timing tests to i2c_model.
// Updated testbench.
//
// Revision 1.2 2002/03/17 10:26:38 rherveille
// Fixed some race conditions in the i2c-slave model.
// Added debug information.
// Added headers.
//
 
`include "timescale.v"
 
module i2c_slave_model (scl, sda);
 
//
// parameters
//
parameter I2C_ADR = 7'b001_0000;
 
//
// input && outpus
//
input scl;
inout sda;
 
//
// Variable declaration
//
wire debug = 1'b1;
 
reg [7:0] mem [3:0]; // initiate memory
reg [7:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
 
reg sta, d_sta;
reg sto, d_sto;
 
reg [7:0] sr; // 8bit shift register
reg rw; // read/write direction
 
wire my_adr; // my address called ??
wire i2c_reset; // i2c-statemachine reset
reg [2:0] bit_cnt; // 3bit downcounter
wire acc_done; // 8bits transfered
reg ld; // load downcounter
 
reg sda_o; // sda-drive level
wire sda_dly; // delayed version of sda
 
// statemachine declaration
parameter idle = 3'b000;
parameter slave_ack = 3'b001;
parameter get_mem_adr = 3'b010;
parameter gma_ack = 3'b011;
parameter data = 3'b100;
parameter data_ack = 3'b101;
 
reg [2:0] state; // synopsys enum_state
 
//
// module body
//
 
initial
begin
sda_o = 1'b1;
state = idle;
end
 
// generate shift register
always @(posedge scl)
sr <= #1 {sr[6:0],sda};
 
//detect my_address
assign my_adr = (sr[7:1] == I2C_ADR);
// FIXME: This should not be a generic assign, but rather
// qualified on address transfer phase and probably reset by stop
 
//generate bit-counter
always @(posedge scl)
if(ld)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
 
//generate access done signal
assign acc_done = !(|bit_cnt);
 
// generate delayed version of sda
// this model assumes a hold time for sda after the falling edge of scl.
// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
// with regards to scl. If the data changes coincident with the clock, the
// acknowledge is missed
// Fix by Michael Sosnoski
assign #1 sda_dly = sda;
 
 
//detect start condition
always @(negedge sda)
if(scl)
begin
sta <= #1 1'b1;
 
if(debug)
$display("DEBUG i2c_slave; start condition detected at %t", $time);
end
else
sta <= #1 1'b0;
 
always @(posedge scl)
d_sta <= #1 sta;
 
// detect stop condition
always @(posedge sda)
if(scl)
begin
sto <= #1 1'b1;
 
if(debug)
$display("DEBUG i2c_slave; stop condition detected at %t", $time);
end
else
sto <= #1 1'b0;
 
//generate i2c_reset signal
assign i2c_reset = sta || sto;
 
// generate statemachine
always @(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
state <= #1 idle; // reset statemachine
 
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;
 
case(state) // synopsys full_case parallel_case
idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b0; // generate i2c_ack
 
#2;
if(debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if(debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
 
if(rw)
begin
mem_do <= #1 mem[mem_adr];
 
if(debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
end
end
end
 
slave_ack:
begin
if(rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
state <= #1 get_mem_adr;
 
ld <= #1 1'b1;
end
 
get_mem_adr: // wait for memory address
if(acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
 
if(debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end
 
gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end
 
data: // receive or drive data
begin
if(rw)
sda_o <= #1 mem_do[7];
 
if(acc_done)
begin
state <= #1 data_ack;
mem_adr <= #2 mem_adr + 8'h1;
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
 
if(rw)
begin
#3 mem_do <= mem[mem_adr];
 
if(debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
end
 
if(!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
 
if(debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
end
end
 
data_ack:
begin
ld <= #1 1'b1;
 
if(rw)
if(sda) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
end
 
endcase
end
 
// read data from memory
always @(posedge scl)
if(!acc_done && rw)
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
 
// generate tri-states
assign sda = sda_o ? 1'bz : 1'b0;
 
 
//
// Timing checks
//
 
wire tst_sto = sto;
wire tst_sta = sta;
 
specify
specparam normal_scl_low = 4700,
normal_scl_high = 4000,
normal_tsu_sta = 4700,
normal_tsu_sto = 4000,
normal_sta_sto = 4700,
 
fast_scl_low = 1300,
fast_scl_high = 600,
fast_tsu_sta = 1300,
fast_tsu_sto = 600,
fast_sta_sto = 1300;
 
$width(negedge scl, normal_scl_low); // scl high time
$width(posedge scl, normal_scl_high); // scl low time
 
$setup(negedge sda &&& scl, negedge scl, normal_tsu_sta); // start condition
$setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // stop condition
 
$setup(posedge tst_sta, posedge tst_sto, normal_sta_sto); // stop to start time
endspecify
 
endmodule
 
 
/verilog/tst_bench_top.v
0,0 → 1,396
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: tst_bench_top.v,v 1.3 2002-10-30 18:11:06 rherveille Exp $
//
// $Date: 2002-10-30 18:11:06 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/03/17 10:26:38 rherveille
// Fixed some race conditions in the i2c-slave model.
// Added debug information.
// Added headers.
//
 
`include "timescale.v"
 
module tst_bench_top();
 
//
// wires && regs
//
reg clk;
reg rstn;
 
wire [31:0] adr;
wire [ 7:0] dat_i, dat_o;
wire we;
wire stb;
wire cyc;
wire ack;
wire inta;
 
reg [7:0] q, qq;
 
wire scl, scl_o, scl_oen;
wire sda, sda_o, sda_oen;
 
parameter PRER_LO = 3'b000;
parameter PRER_HI = 3'b001;
parameter CTR = 3'b010;
parameter RXR = 3'b011;
parameter TXR = 3'b011;
parameter CR = 3'b100;
parameter SR = 3'b100;
 
parameter TXR_R = 3'b101; // undocumented / reserved output
parameter CR_R = 3'b110; // undocumented / reserved output
 
//
// Module body
//
 
// generate clock
always #5 clk = ~clk;
 
// hookup wishbone master model
wb_master_model #(8, 32) u0 (
.clk(clk),
.rst(rstn),
.adr(adr),
.din(dat_i),
.dout(dat_o),
.cyc(cyc),
.stb(stb),
.we(we),
.sel(),
.ack(ack),
.err(1'b0),
.rty(1'b0)
);
 
// hookup wishbone_i2c_master core
i2c_master_top i2c_top (
 
// wishbone interface
.wb_clk_i(clk),
.wb_rst_i(1'b0),
.arst_i(rstn),
.wb_adr_i(adr[2:0]),
.wb_dat_i(dat_o),
.wb_dat_o(dat_i),
.wb_we_i(we),
.wb_stb_i(stb),
.wb_cyc_i(cyc),
.wb_ack_o(ack),
.wb_inta_o(inta),
 
// i2c signals
.scl_pad_i(scl),
.scl_pad_o(scl_o),
.scl_padoen_o(scl_oen),
.sda_pad_i(sda),
.sda_pad_o(sda_o),
.sda_padoen_o(sda_oen)
);
 
// hookup i2c slave model
i2c_slave_model #(7'b1010_000) i2c_slave (
.scl(scl),
.sda(sda)
);
 
// create i2c lines
assign scl = scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
assign sda = sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
 
pullup p1(scl); // pullup scl line
pullup p2(sda); // pullup sda line
 
initial
begin
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",tst_bench_top,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
 
// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
$display("\nstatus: %t Testbench started\n\n", $time);
 
// $dumpfile("bench.vcd");
// $dumpvars(1, tst_bench_top);
// $dumpvars(1, tst_bench_top.i2c_slave);
 
// initially values
clk = 0;
 
// reset system
rstn = 1'b1; // negate reset
#2;
rstn = 1'b0; // assert reset
repeat(20) @(posedge clk);
rstn = 1'b1; // negate reset
 
$display("status: %t done reset", $time);
 
@(posedge clk);
 
//
// program core
//
 
// program internal registers
// u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
$display("status: %t programmed registers", $time);
 
u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
$display("status: %t verified registers", $time);
 
u0.wb_write(1, CTR, 8'h80); // enable core
$display("status: %t core enabled", $time);
 
//
// access slave (write)
//
 
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave memory address 01", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// send memory contents
u0.wb_write(1, TXR, 8'ha5); // present data
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write data a5", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// send memory contents for next memory address (auto_inc)
u0.wb_write(1, TXR, 8'h5a); // present data
u0.wb_write(0, CR, 8'h50); // set command (stop, write)
$display("status: %t write next data 5a, generate 'stop'", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
//
// delay
//
// #100000; // wait for 100us.
// $display("status: %t wait 100us", $time);
 
//
// access slave (read)
//
 
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave address 01", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// drive slave address
u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
if(qq !== 8'ha5)
$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
 
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
if(qq !== 8'h5a)
$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
 
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 3rd read address", $time, qq);
 
// read data from slave
u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
$display("status: %t read + nack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 4th read address", $time, qq);
 
//
// check invalid slave memory address
//
 
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// send memory address
u0.wb_write(1, TXR, 8'h10); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave memory address 10", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// slave should have send NACK
$display("status: %t Check for nack", $time);
if(!q[7])
$display("\nERROR: Expected NACK, received ACK\n");
 
// read data from slave
u0.wb_write(1, CR, 8'h40); // set command (stop)
$display("status: %t generate 'stop'", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
#25000; // wait 25us
$display("\n\nstatus: %t Testbench done", $time);
$finish;
end
 
endmodule
 
 
/verilog/wb_master_model.v
0,0 → 1,205
///////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 Wishbone Master model ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
//// ////
///////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
///////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_master_model.v,v 1.2 2002-03-17 10:26:38 rherveille Exp $
//
// $Date: 2002-03-17 10:26:38 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
//
`include "timescale.v"
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
parameter dwidth = 32;
parameter awidth = 32;
 
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dwidth/8 -1:0] sel;
input ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg cyc, stb;
reg we;
reg [dwidth/8 -1:0] sel;
 
reg [dwidth -1:0] q;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
input delay;
integer delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
// assert wishbone signal
#1;
adr = a;
dout = d;
cyc = 1'b1;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
while(~ack) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
input delay;
integer delay;
 
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
// assert wishbone signals
#1;
adr = a;
dout = {dwidth{1'bx}};
cyc = 1'b1;
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
while(~ack) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
 
task wb_cmp;
input delay;
integer delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read (delay, a, q);
 
if (d_exp !== q)
$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
end
endtask
 
endmodule
 
 

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