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Rev 2 → Rev 3

/src/i2c_to_wb_fsm.v
0,0 → 1,177
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
`include "timescale.v"
 
 
module
i2c_to_wb_fsm
(
input i2c_data,
input i2c_data_rise,
input i2c_data_fall,
 
input i2c_clk,
input i2c_clk_rise,
input i2c_clk_fall,
input i2c_bit_7,
output i2c_ack_done,
output tip_addr_byte,
// output tip_byte,
output tip_read_byte,
output tip_write_byte,
output tip_wr_ack,
output tip_rd_ack,
output tip_addr_ack,
// output tip_ack,
// output tip_write,
// output tip_read,
output [7:0] state_out,
input wb_clk_i,
input wb_rst_i
);
// --------------------------------------------------------------------
// wires
wire xmt_byte_done;
// wire i2c_read = 1'b0;
// wire i2c_ack_done;
wire i2c_address_hit = 1'b1;
wire tip_ack;
 
// --------------------------------------------------------------------
// start & stop
wire start_detected = i2c_data_fall & i2c_clk;
wire stop_detected = i2c_data_rise & i2c_clk;
// --------------------------------------------------------------------
// state machine
 
localparam STATE_IDLE = 8'b00000001;
localparam STATE_ADDR_BYTE = 8'b00000010;
localparam STATE_ADDR_ACK = 8'b00000100;
localparam STATE_WRITE = 8'b00001000;
localparam STATE_WR_ACK = 8'b00010000;
localparam STATE_READ = 8'b00100000;
localparam STATE_RD_ACK = 8'b01000000;
localparam STATE_ERROR = 8'b10000000;
 
reg [7:0] state;
reg [7:0] next_state;
always @(posedge wb_clk_i or posedge wb_rst_i)
if(wb_rst_i)
state <= STATE_IDLE;
else
state <= next_state;
 
always @(*)
case( state )
STATE_IDLE: if( start_detected )
next_state = STATE_ADDR_BYTE;
else
next_state = STATE_IDLE;
STATE_ADDR_BYTE: if( xmt_byte_done )
if( i2c_address_hit )
next_state = STATE_ADDR_ACK;
else
next_state = STATE_IDLE;
else if( start_detected | stop_detected )
next_state = STATE_ERROR;
else
next_state = STATE_ADDR_BYTE;
STATE_ADDR_ACK: if( i2c_ack_done )
if( i2c_bit_7 )
next_state = STATE_READ;
else
next_state = STATE_WRITE;
else if( start_detected | stop_detected )
next_state = STATE_ERROR;
else
next_state = STATE_ADDR_ACK;
STATE_WRITE: if( xmt_byte_done )
next_state = STATE_WR_ACK;
else if( start_detected )
next_state = STATE_ADDR_BYTE;
else if( stop_detected )
next_state = STATE_IDLE;
else
next_state = STATE_WRITE;
STATE_WR_ACK: if( i2c_ack_done )
next_state = STATE_WRITE;
else if( start_detected | stop_detected )
next_state = STATE_ERROR;
else
next_state = STATE_WR_ACK;
STATE_READ: if( xmt_byte_done )
next_state = STATE_RD_ACK;
else if( start_detected )
next_state = STATE_ADDR_BYTE;
else if( stop_detected )
next_state = STATE_IDLE;
else
next_state = STATE_READ;
STATE_RD_ACK: if( i2c_ack_done )
next_state = STATE_READ;
else if( start_detected | stop_detected )
next_state = STATE_ERROR;
else
next_state = STATE_RD_ACK;
STATE_ERROR: next_state = STATE_IDLE;
default: next_state = STATE_ERROR;
endcase
// --------------------------------------------------------------------
// bit counter
reg [3:0] bit_count;
assign xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;
assign tip_ack = (bit_count == 4'h8);
assign i2c_ack_done = tip_ack & i2c_clk_rise;
always @(posedge wb_clk_i)
if( wb_rst_i | i2c_ack_done | start_detected )
bit_count <= 4'hf;
else if( i2c_clk_fall )
bit_count <= bit_count + 1;
// --------------------------------------------------------------------
// outputs
assign state_out = state;
assign tip_addr_byte = (state == STATE_ADDR_BYTE);
assign tip_addr_ack = (state == STATE_ADDR_ACK);
assign tip_read_byte = (state == STATE_READ);
assign tip_write_byte = tip_addr_byte | (state == STATE_WRITE);
assign tip_wr_ack = tip_addr_ack | (state == STATE_WR_ACK);
assign tip_rd_ack = (state == STATE_RD_ACK);
// assign tip_byte = tip_write_byte | tip_read_byte;
// assign tip_write = tip_write_byte | tip_wr_ack;
// assign tip_read = tip_read_byte | tip_rd_ack;
endmodule
 
/src/i2c_to_wb_top.v
10,7 → 10,7
i2c_to_wb_top
#(
parameter DW = 32,
parameter AW = 32
parameter AW = 8
)
(
input i2c_data_in,
19,6 → 19,8
output i2c_clk_out,
output i2c_data_oe,
output i2c_clk_oe,
input [3:0] thd_dat,
 
input [(DW-1):0] wb_data_i,
output [(DW-1):0] wb_data_o,
35,8 → 37,23
input wb_rst_i
);
 
// --------------------------------------------------------------------
// wires
// wire tip_byte;
wire tip_addr_byte;
wire tip_read_byte;
wire tip_write_byte;
wire tip_wr_ack;
wire tip_rd_ack;
wire tip_addr_ack;
// wire tip_ack;
// wire tip_write;
// wire tip_read;
wire i2c_ack_out = 1'b0;
wire i2c_ack_done;
// --------------------------------------------------------------------
// glitch filter
wire gf_i2c_data_in;
73,71 → 90,96
// --------------------------------------------------------------------
// bit counter
reg [3:0] bit_count;
wire ack_done = (bit_count > 4'h8) & gf_i2c_clk_in_rise;
// i2c data
always @(posedge wb_clk_i or posedge wb_rst_i)
if( wb_rst_i | ack_done )
bit_count <= 4'h0;
else if( gf_i2c_clk_in_fall )
bit_count <= bit_count + 1;
// --------------------------------------------------------------------
// start & stop
reg [8:0] i2c_data_in_r; // add throw away bit for serial_out
reg parallel_load_r;
wire parallel_load = ~parallel_load_r & tip_read_byte;
wire [7:0] parallel_load_data = 8'h11;
wire serial_out = i2c_data_in_r[8];
reg gf_i2c_data_in_fall_reg;
always @(posedge wb_clk_i)
gf_i2c_data_in_fall_reg <= gf_i2c_data_in_fall;
parallel_load_r <= tip_read_byte;
reg gf_i2c_data_in_rise_reg;
always @(posedge wb_clk_i)
gf_i2c_data_in_rise_reg <= gf_i2c_data_in_rise;
wire start_detected = gf_i2c_data_in_fall_reg & gf_i2c_clk_in;
wire stop_detected = gf_i2c_data_in_rise_reg & gf_i2c_clk_in;
if( parallel_load )
i2c_data_in_r[7:0] <= parallel_load_data;
else if( (tip_write_byte & gf_i2c_clk_in_rise) | (tip_read_byte & gf_i2c_clk_in_fall) )
i2c_data_in_r <= {i2c_data_in_r[7:0], gf_i2c_data_in};
// --------------------------------------------------------------------
// transmition in progress
// wishbone stuff
reg tip_slave_address;
reg [7:0] i2c_address_r;
always @(posedge wb_clk_i)
if( ack_done | wb_rst_i )
tip_slave_address <= 1'b0;
else if( start_detected )
tip_slave_address <= 1'b1;
if( tip_addr_ack )
i2c_address_r <= 8'h00;
else if( i2c_ack_done )
i2c_address_r <= i2c_address_r + 1;
reg tip;
 
// --------------------------------------------------------------------
// state machine
i2c_to_wb_fsm
i_i2c_to_wb_fsm
(
.i2c_data(gf_i2c_data_in),
.i2c_data_rise(gf_i2c_data_in_rise),
.i2c_data_fall(gf_i2c_data_in_fall),
always @(posedge wb_clk_i)
if( wb_rst_i )
tip <= 0;
else if( start_detected | stop_detected )
tip <= start_detected;
.i2c_clk(gf_i2c_clk_in),
.i2c_clk_rise(gf_i2c_clk_in_rise),
.i2c_clk_fall(gf_i2c_clk_in_fall),
wire bit_ack_detected = (bit_count == 4'h9) & tip;
.i2c_bit_7(i2c_data_in_r[7]),
.i2c_ack_done(i2c_ack_done),
.tip_addr_byte(tip_addr_byte),
// .tip_byte(tip_byte),
.tip_read_byte(tip_read_byte),
.tip_write_byte(tip_write_byte),
.tip_wr_ack(tip_wr_ack),
.tip_rd_ack(tip_rd_ack),
.tip_addr_ack(tip_addr_ack),
// .tip_ack(tip_ack),
// .tip_write(tip_write),
// .tip_read(tip_read),
.state_out(),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i)
);
// --------------------------------------------------------------------
// ack flop
reg ack_bit_r;
// i2c_data out sync
reg i2c_data_oe_r;
always @(posedge wb_clk_i)
if( wb_rst_i )
ack_bit_r <= 1'b0;
else if( bit_ack_detected & gf_i2c_clk_in_fall )
ack_bit_r <= i2c_data_in;
i2c_data_oe_r <= 1'b0;
else if( gf_i2c_clk_in_fall )
i2c_data_oe_r <= tip_read_byte | tip_wr_ack;
reg i2c_data_mux_select_r;
always @(posedge wb_clk_i)
if( gf_i2c_clk_in_fall )
i2c_data_mux_select_r <= tip_wr_ack;
// --------------------------------------------------------------------
// outputs
assign i2c_data_out = 1'b1;
assign i2c_data_out = i2c_data_mux_select_r ? i2c_ack_out : serial_out;
assign i2c_data_oe = i2c_data_oe_r;
assign i2c_clk_out = 1'b1;
assign i2c_data_oe = 1'b0;
assign i2c_clk_oe = 1'b0;
assign wb_cyc_o = tip_wr_ack | tip_rd_ack;
assign wb_addr_o[7:0] = i2c_address_r;
assign wb_we_o = tip_wr_ack;
 
endmodule
/sim/tests/debug/the_test.v
18,11 → 18,11
// insert test below
 
dut.i2c.start();
dut.i2c.write_byte( 8'h00 );
dut.i2c.write_byte( 8'h10 );
dut.i2c.write_byte( 8'hff );
dut.i2c.start();
dut.i2c.write_byte( 8'haa );
dut.i2c.write_byte( 8'hcb );
dut.i2c.read_byte();
dut.i2c.stop();
/sim/tests/debug/debug.mpf
408,21 → 408,23
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 7
Project_Files_Count = 8
Project_File_0 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/tests/debug/the_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1273798997 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1283381708 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/models/i2c_master_model.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1274199521 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1283295745 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/models/glitch_generator.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1273796060 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/i2c_to_wb/src/i2c_to_wb_top.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1274200851 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/src/tb_dut.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1273796392 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/i2c_to_wb/src/glitch_filter.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1273795452 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/src/tb_top.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1273187085 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/i2c_to_wb/src/i2c_to_wb_fsm.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1283388466 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/i2c_to_wb/src/i2c_to_wb_top.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1283389102 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/src/tb_dut.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1283366916 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/i2c_to_wb/src/glitch_filter.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1273795452 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/i2c_to_wb/sim/src/tb_top.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1273187085 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
/sim/models/i2c_master_model.v
18,7 → 18,7
localparam tBUF = 4700;
localparam tSU_STA = 4700;
localparam tSU_DAT = 250;
localparam tHD_DAT = 0;
localparam tHD_DAT = 300;
localparam tHD_STA = 4000;
localparam tLOW = 4700;
localparam tHIGH = 4000;
55,8 → 55,8
if( LOG_LEVEL > 2 )
$display( "###- %m: I2C start at time %t. ", $time );
i2c_data_out = 1'b1;
i2c_clk_out = 1'b1;
// i2c_data_out = 1'b1;
// i2c_clk_out = 1'b1;
#tBUF;
72,7 → 72,7
if( i2c_clk != 1'b1 )
begin
i2c_clk_out = 1'b1;
#tSU_DAT;
#tLOW;
end
#tSU_STA;
99,7 → 99,7
if( i2c_clk != 1'b1 )
begin
i2c_clk_out = 1'b1;
#tSU_DAT;
#tLOW;
end
i2c_data_out = 1'b1;
134,10 → 134,14
// --------------------------------------------------------------------
// write_byte
reg write_byte_r = 1'b0;
task write_byte;
input [7:0] data;
begin
write_byte_r = 1'b1;
if( LOG_LEVEL > 2 )
$display( "###- %m: I2C write 0x%h at time %t. ", data, $time );
169,6 → 173,10
$display( "###- %m: I2C ACK at time %t. ", $time );
#tHIGH;
i2c_clk_out = 1'b0;
write_byte_r = 1'b0;
#1;
end
endtask
225,6 → 233,9
if( LOG_LEVEL > 2 )
$display( "###- %m: I2C read 0x%h at time %t. ", i2c_buffer_in, $time );
#tHIGH;
i2c_clk_out = 1'b0;
end
endtask
/sim/src/tb_dut.v
41,7 → 41,7
wire i2c_clk_out;
wire i2c_data_oe;
wire i2c_clk_oe;
wire [31:0] wb_data_i;
wire [31:0] wb_data_i = 32'ha5a5a5a5;
wire [31:0] wb_data_o;
wire [31:0] wb_addr_o;
wire [3:0] wb_sel_o;
48,9 → 48,9
wire wb_we_o;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_ack_i;
wire wb_err_i;
wire wb_rty_i;
wire wb_ack_i = 1'b1;
wire wb_err_i = 1'b0;
wire wb_rty_i = 1'b0;
// tristate buffers
assign i2c_data = i2c_data_oe ? i2c_data_out : 1'bz;
64,6 → 64,8
.i2c_clk_out(i2c_clk_out),
.i2c_data_oe(i2c_data_oe),
.i2c_clk_oe(i2c_clk_oe),
.thd_dat(4'h8),
.wb_data_i(wb_data_i),
.wb_data_o(wb_data_o),

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