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URL https://opencores.org/ocsvn/i2cslave/i2cslave/trunk

Subversion Repositories i2cslave

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  • This comparison shows the changes necessary to convert path 
    /i2cslave/trunk/Aldec/design0
    from Rev 2 to Rev 5
    ↔ Reverse comparison
  •

Rev 2 → Rev 5

/fsm.set
0,0 → 1,5
FSMSET_CUTHEADER=1
FSMSET_GENCOMMENTS=1
FSMSET_USEDEFINE=1
FSMSET_OMITGENNULL=0
FSMSET_ENABLEPARSING=1
/design0.adf
0,0 → 1,28
[Project]
Current Flow=Generic
VCS=0
version=1
Current Config=compile
 
[Configurations]
compile=design0
 
[Library]
design0=.\design0.LIB
 
[$LibMap$]
design0=.
 
[Settings]
FLOW_TYPE=HDL
LANGUAGE=VHDL
 
[Files]
/serialInterface.asf=-1
 
[Files.Data]
.\src\serialInterface.asf=State Diagram
 
[file_out:/serialInterface.asf]
/\compile\serialInterface.v=-1
 
/src/serialInterface.asf
0,0 → 1,207
VERSION=1.15
HEADER
FILE="serialInterface.asf"
FID=4788d213
LANGUAGE=VERILOG
ENTITY="serialInterface"
FRAMES=ON
FREEOID=1240
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// serialInterface.v ////\n//// ////\n//// This file is part of the i2cSlave opencores effort.\n//// <http://www.opencores.org/cores//> ////\n//// ////\n//// Module Description: ////\n//// Perform all serial to parallel, and parallel\n//// to serial conversions. Perform device address matching\n//// Handle arbitrary length I2C reads terminated by NAK\n//// from host, and arbitrary length I2C writes terminated\n//// by STOP from host\n//// The second byte of a I2C write is always interpreted\n//// as a register address, and becomes the base register address\n//// for all read and write transactions.\n//// I2C WRITE: devAddr, regAddr, data[regAddr], data[regAddr+1], ..... data[regAddr+N]\n//// I2C READ: data[regAddr], data[regAddr+1], ..... data[regAddr+N]\n//// Note that when regAddR reaches 255 it will automatically wrap round to 0\n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from <http://www.opencores.org/lgpl.shtml> ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"i2cSlave_define.v\"\n"
END
BUNDLES
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 2844 0 0000 1 "Arial" 0
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 2844 0 0110 1 "Arial" 0
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0
B T "Actions" 0,0,0 0 0 1 255,255,255 0 2844 0 0000 1 "Arial" 0
B T "Labels" 0,0,0 0 0 0 255,255,255 0 2844 0 0000 1 "Arial" 0
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0
B T "State Labels" 0,0,0 0 0 0 255,255,255 0 2844 0 0000 1 "Arial" 4
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0
END
INSTHEADER 1
PAGE 25400,25400 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 5000,5000 10000,10000
END
INSTHEADER 1093
PAGE 25400,25400 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 0,0 10000,10000
END
INSTHEADER 1102
PAGE 25400,25400 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 0,0 10000,10000
END
INSTHEADER 1163
PAGE 25400,25400 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 0,0 10000,10000
END
OBJECTS
L 7 6 0 TEXT "Labels" | 31673,209974 1 0 0 "SISt"
F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,212603
A 5 0 1 TEXT "Actions" | 30400,266783 1 0 0 "-- diagram ACTION"
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: serialInterface"
I 1088 0 130 Builtin Signal | 170556,231962 "" ""
A 1089 100 4 TEXT "Actions" | 164916,210687 1 0 0 "streamSt <= `STREAM_IDLE;\ntxData <= 8'h00;\nrxData <= 8'h00;\nsdaOut <= 1'b1;\nwriteEn <= 1'b0;\ndataOut <= 8'h00;\nbitCnt <= 3'b000;\nclearStartStopDet <= 1'b0;"
L 1090 1091 0 TEXT "State Labels" | 113022,167010 1 0 0 "CHK_RD_WR\n/1/"
S 1091 6 4096 ELLIPSE "States" | 113022,167010 6500 6500
L 1092 1093 0 TEXT "State Labels" | 145788,131922 1 0 0 "READ"
S 1093 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 145788,131922 6500 6500
H 1094 1093 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
I 1097 1094 0 Builtin Entry | 45436,264408
I 1098 1094 0 Builtin Exit | 66804,75108
L 1101 1102 0 TEXT "State Labels" | 82836,130374 1 0 0 "WRITE"
S 1102 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 82836,130374 6500 6500
H 1103 1102 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
I 1106 1103 0 Builtin Entry | 45436,269052
W 1111 6 1 1091 1093 BEZIER "Transitions" | 117575,162372 124283,155471 134905,143802 141613,136901
W 1112 6 2 1091 1102 BEZIER "Transitions" | 108455,162386 102521,154775 92600,143235 86666,135624
C 1113 1111 0 TEXT "Conditions" | 124761,159657 1 0 0 "streamSt == `STREAM_READ"
L 1114 1115 0 TEXT "State Labels" | 60132,233832 1 0 0 "RD_LOOP\n/2/"
S 1115 1094 16384 ELLIPSE "States" | 60132,233832 6500 6500
W 1116 1094 0 1097 1115 BEZIER "Transitions" | 49435,264408 51757,258345 54648,245572 56970,239509
L 1117 1118 0 TEXT "State Labels" | 62196,202356 1 0 0 "WT_HI\n/3/"
S 1118 1094 20480 ELLIPSE "States" | 62196,202356 6500 6500
W 1119 1094 0 1115 1118 BEZIER "Transitions" | 60334,227358 60656,222198 61220,213982 61542,208822
C 1120 1119 0 TEXT "Conditions" | 61814,227496 1 0 0 "scl == 1'b0"
L 1121 1122 0 TEXT "State Labels" | 63833,168493 1 0 0 "CHK_LOOP_FIN\n/4/"
S 1122 1094 24576 ELLIPSE "States" | 63833,168493 6500 6500
W 1123 1094 0 1118 1122 BEZIER "Transitions" | 62616,195885 62873,192095 63548,178990 63552,174971
C 1124 1123 0 TEXT "Conditions" | 65004,194763 1 0 0 "scl == 1'b1"
A 1125 1116 16 TEXT "Actions" | 46574,259544 1 0 0 "txData <= dataIn;\nregAddr <= regAddr + 1'b1;\nbitCnt <= 3'b001;"
L 1127 1128 0 TEXT "State Labels" | 64515,139815 1 0 0 "WT_LO\n/5/"
S 1128 1094 28672 ELLIPSE "States" | 64515,139815 6500 6500
W 1133 1094 1 1122 1128 BEZIER "Transitions" | 63734,162016 63671,157426 63956,150868 63893,146278
C 1135 1133 0 TEXT "Conditions" | 67448,161363 1 0 0 "bitCnt == 3'b000"
W 1136 1094 2 1122 1115 BEZIER "Transitions" | 70264,169432 80793,170973 95664,170699 106435,174896\
117206,179094 120169,183293 119563,193014 118958,202736\
113857,211534 106441,217176 99026,222818 76882,233683\
66172,236233
L 1137 1138 0 TEXT "State Labels" | 65790,108960 1 0 0 "WT_ACK\n/6/"
S 1138 1094 32768 ELLIPSE "States" | 65790,108960 6500 6500
W 1139 1094 0 1128 1138 BEZIER "Transitions" | 64641,133339 64223,128449 65212,119705 65696,115446
A 1141 1136 16 TEXT "Actions" | 99952,191787 1 0 0 "bitCnt <= bitCnt + 1'b1;"
A 1143 1119 16 TEXT "Actions" | 42458,221543 1 0 0 "sdaOut <= txData [7];\ntxData <= {txData [6:0], 1'b0};"
C 1144 1139 0 TEXT "Conditions" | 66481,131783 1 0 0 "scl == 1'b0"
W 1147 1094 0 1138 1098 BEZIER "Transitions" | 65848,102499 65911,97591 66741,82032 66804,77124
C 1148 1147 0 TEXT "Conditions" | 67234,101707 1 0 0 "scl == 1'b1"
A 1149 1147 16 TEXT "Actions" | 61593,95455 1 0 0 "if (sdaIn == `I2C_NAK)\n streamSt <= `STREAM_IDLE;"
A 1150 1139 16 TEXT "Actions" | 63113,125918 1 0 0 "sdaOut <= 1'b1;"
L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk"
I 72 0 3 Builtin InPort | 195700,272800 "" ""
L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst"
I 74 0 2 Builtin InPort | 195700,267632 "" ""
L 1152 1153 0 TEXT "State Labels" | 50328,243636 1 0 0 "WT_HI\n/8/"
S 1153 1103 45056 ELLIPSE "States" | 50328,243636 6500 6500
W 1154 1103 0 1106 1153 BEZIER "Transitions" | 45436,266988 46403,261957 48180,255054 49147,250023
L 1156 1157 0 TEXT "State Labels" | 53682,211902 1 0 0 "WT_LO\n/7/"
S 1157 1103 40960 ELLIPSE "States" | 53682,211902 6500 6500
W 1158 1103 0 1153 1157 BEZIER "Transitions" | 50941,237173 51263,234013 52778,221621 52602,218309
C 1160 1158 0 TEXT "Conditions" | 52521,236757 1 0 0 "scl == 1'b1"
L 1162 1163 0 TEXT "State Labels" | 54198,183780 1 0 0 "J1"
S 1163 1103 36868 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 54136,183976 3858 3858
W 1164 1103 0 1157 1163 BEZIER "Transitions" | 53938,205422 54389,199424 52869,194235 53483,187777
C 1165 1164 0 TEXT "Conditions" | 36280,204549 1 0 0 "scl == 1'b0"
H 1166 1163 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
I 1169 1166 0 Builtin Entry | 96520,182880
I 1170 1166 0 Builtin Exit | 144780,121920
W 1171 1166 0 1169 1170 BEZIER "Transitions" | 100503,182880 105961,175176 136367,129625 141825,121920
C 1174 1173 0 TEXT "Conditions" | 38599,178519 1 0 0 "startStopDetState == `STOP_DET || \n(streamSt == `STREAM_IDLE && startStopDetState == `NULL_DET)"
A 1175 1158 16 TEXT "Actions" | 50457,231381 1 0 0 "rxData <= {rxData [6:0], sdaIn};\nbitCnt <= 3'b000;"
L 1176 1177 0 TEXT "State Labels" | 153270,180426 1 0 0 "ST_LOOP\n/11/"
S 1177 1103 57344 ELLIPSE "States" | 153270,180426 6500 6500
W 1178 1103 2 1163 1177 BEZIER "Transitions" | 57992,183868 81212,183352 123565,181370 146785,180854
L 1179 1180 0 TEXT "State Labels" | 155592,146628 1 0 0 "LOOP_WT_LO\n/10/"
S 1180 1103 53248 ELLIPSE "States" | 155592,146628 6500 6500
L 1181 1182 0 TEXT "State Labels" | 157656,119022 1 0 0 "CHK_LOOP_FIN\n/9/"
S 1182 1103 49152 ELLIPSE "States" | 157656,119022 6500 6500
W 1183 1103 0 1177 1180 BEZIER "Transitions" | 153480,173948 154060,169433 154616,157853 155339,153110
W 1173 1103 1 1163 1227 BEZIER "Transitions" | 53628,180156 50790,158613 43756,133955 42667,107411
L 99 100 0 TEXT "State Labels" | 112176,193512 1 0 0 "START\n/0/"
S 100 6 0 ELLIPSE "States" | 112176,193512 6500 6500
C 1184 1183 0 TEXT "Conditions" | 155746,173950 1 0 0 "scl == 1'b1"
A 1185 1183 16 TEXT "Actions" | 132915,164958 1 0 0 "rxData <= {rxData [6:0], sdaIn};"
W 1186 1103 0 1180 1182 BEZIER "Transitions" | 155830,140145 156152,136275 156699,129381 156919,125472
C 1187 1186 0 TEXT "Conditions" | 157807,138966 1 0 0 "scl == 1'b0"
L 1188 1189 0 TEXT "State Labels" | 140079,63027 1 0 0 "WT_HI2\n/13/"
S 1189 1103 65536 ELLIPSE "States" | 140079,63027 6500 6500
W 1190 1103 1 1182 1222 BEZIER "Transitions" | 158063,112542 158373,105705 114008,67631 99616,51225
C 1191 1190 0 TEXT "Conditions" | 154327,105370 1 0 0 "bitCnt == 3'b111"
W 1192 1103 2 1182 1177 BEZIER "Transitions" | 164050,120187 172177,122186 187713,125537 192034,132825\
196356,140113 197388,165269 194840,174814 192293,184360\
181069,197390 175554,198486 170040,199583 161883,190407\
156465,186086
A 1194 1192 16 TEXT "Actions" | 177909,132825 1 0 0 "bitCnt <= bitCnt + 1'b1;"
A 1195 1190 16 TEXT "Actions" | 75201,159471 1 0 0 "sdaOut <= `I2C_ACK;\ncase (streamSt)\n `STREAM_IDLE: begin\n if (rxData[7:1] == `I2C_ADDRESS && \n startStopDetState == `START_DET) begin\n if (rxData[0] == 1'b1)\n streamSt <= `STREAM_READ;\n else\n streamSt <= `STREAM_WRITE_ADDR;\n end\n else\n sdaOut <= `I2C_NAK;\n end\n `STREAM_WRITE_ADDR: begin\n streamSt <= `STREAM_WRITE_DATA;\n regAddr <= rxData;\n end\n `STREAM_WRITE_DATA: begin\n dataOut <= rxData;\n writeEn <= 1'b1;\n end\n default:\n streamSt <= streamSt; \nendcase"
L 1196 1197 0 TEXT "State Labels" | 191305,78543 1 0 0 "WT_LO2\n/12/"
S 1197 1103 61440 ELLIPSE "States" | 191305,78543 6500 6500
W 1198 1103 0 1189 1197 BEZIER "Transitions" | 146335,64787 154139,63625 179557,72674 185403,75822
C 1199 1198 0 TEXT "Conditions" | 155872,71869 1 0 0 "scl == 1'b1"
W 1211 6 0 1102 1091 BEZIER "Transitions" | 76391,131214 68980,132010 55006,133664 50535,137890\
46064,142116 43001,157429 45206,164043 47411,170658\
59294,181807 66276,184103 73258,186400 89307,184440\
95064,182296 100821,180153 105473,175392 108964,172085
W 1210 6 0 1093 1091 BEZIER "Transitions" | 152177,133113 160752,135501 176220,139177 178823,144934\
181427,150691 174688,168944 167277,174211 159867,179478\
136958,182297 130006,181531 123055,180765 119021,175394\
116571,172454
I 1209 0 130 Builtin Signal | 170935,221379 "" ""
L 1208 1209 0 TEXT "Labels" | 173935,221379 1 0 0 "rxData[7:0]"
I 1207 0 130 Builtin Signal | 170682,226692 "" ""
L 1206 1207 0 TEXT "Labels" | 173682,226692 1 0 0 "txData[7:0]"
I 387 6 0 Builtin Reset | 49555,202550
W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019
C 389 388 0 TEXT "Conditions" | 63836,205024 1 0 0 "rst == 1'b1"
W 1201 1103 0 1197 1228 BEZIER "Transitions" | 192418,72141 193381,63146 199794,43721 197819,33702
C 1202 1201 0 TEXT "Conditions" | 186842,58803 1 0 0 "scl == 1'b0"
A 1203 1173 16 TEXT "Actions" | 31827,161251 1 0 0 "streamSt <= `STREAM_IDLE;\nclearStartStopDet <= 1'b1;"
A 1205 1154 16 TEXT "Actions" | 46743,263198 1 0 0 "rxData <= 8'h00;"
L 1212 1213 0 TEXT "Labels" | 173176,236812 1 0 0 "bitCnt[2:0]"
I 1213 0 130 Builtin Signal | 170176,236812 "" ""
L 1215 1216 0 TEXT "Labels" | 82738,249858 1 0 0 "clearStartStopDet"
I 1216 0 2 Builtin OutPort | 76738,249858 "" ""
A 1218 1164 16 TEXT "Actions" | 61717,219098 1 0 0 "case (startStopDetState)\n `NULL_DET:\n bitCnt <= bitCnt + 1'b1;\n `START_DET: begin\n streamSt <= `STREAM_IDLE;\n rxData <= 8'h00;\n end\n default: ;\nendcase"
A 1219 1201 16 TEXT "Actions" | 186936,64587 1 0 0 "sdaOut <= 1'b1;"
L 1221 1222 0 TEXT "State Labels" | 97155,45210 1 0 0 "CLR_WR\n/14/"
S 1222 1103 69632 ELLIPSE "States" | 97155,45210 6500 6500
A 1223 1222 4 TEXT "Actions" | 51543,60237 1 0 0 "if (writeEn == 1'b1)\n regAddr <= regAddr + 1'b1;\nwriteEn <= 1'b0;\nclearStartStopDet <= 1'b1;"
W 1224 1103 0 1222 1189 BEZIER "Transitions" | 103397,43398 108943,43589 118129,42724 122750,44891\
127372,47058 132685,53538 136382,57681
A 1225 1189 4 TEXT "Actions" | 138593,50693 1 0 0 "clearStartStopDet <= 1'b0;"
L 1226 1227 0 TEXT "State Labels" | 44784,101266 1 0 0 "CLR_ST_STOP\n/15/"
S 1227 1103 73728 ELLIPSE "States" | 44784,101266 6500 6500
I 1228 1103 0 Builtin Exit | 194898,33702
W 1229 1103 0 1227 1228 BEZIER "Transitions" | 43558,94885 41209,84027 36973,63356 36338,55800\
35703,48244 37863,39734 41355,37226 44847,34718\
56659,33194 75867,32940 95076,32686 159465,33448\
191977,33702
A 1230 1227 4 TEXT "Actions" | 30606,92250 1 0 0 "clearStartStopDet <= 1'b0;"
W 1239 6 0 100 1091 BEZIER "Transitions" | 112488,187021 112665,183009 112810,177405 112987,173393
I 479 0 130 Builtin InPort | 123454,253473 "" ""
L 478 477 0 TEXT "Labels" | 127232,248761 1 0 0 "dataOut[7:0]"
I 477 0 130 Builtin OutPort | 121232,248761 "" ""
L 476 475 0 TEXT "Labels" | 127470,243915 1 0 0 "writeEn"
I 475 0 2 Builtin OutPort | 121470,243915 "" ""
L 472 471 0 TEXT "Labels" | 126974,258272 1 0 0 "regAddr[7:0]"
I 471 0 130 Builtin OutPort | 120974,258272 "" ""
L 480 479 0 TEXT "Labels" | 129454,253473 1 0 0 "dataIn[7:0]"
I 499 0 2 Builtin InPort | 79523,242127 "" ""
L 498 499 0 TEXT "Labels" | 85523,242127 1 0 0 "scl"
I 497 0 130 Builtin InPort | 78578,254745 "" ""
L 496 497 0 TEXT "Labels" | 84578,254745 1 0 0 "startStopDetState[1:0]"
I 1065 0 2 Builtin InPort | 79622,237762 "" ""
L 1064 1065 0 TEXT "Labels" | 85622,237762 1 0 0 "sdaIn"
L 1083 1084 0 TEXT "Labels" | 83208,232994 1 0 0 "sdaOut"
I 1084 0 2 Builtin OutPort | 77208,232994 "" ""
L 1087 1088 0 TEXT "Labels" | 173556,231962 1 0 0 "streamSt[1:0]"
END

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