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- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/zero_check.v
0,0 → 1,58
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// IBM 650 Reconstruction in Verilog (i650) |
// |
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project |
// http:////www.opencores.org/project,i650 |
// |
// Description: Accumulator zero check. |
// |
// Additional Comments: See US 2959351, Fig. 84. |
// |
// Copyright (c) 2015 Robert Abeles |
// |
// This source file is free software; you can redistribute it |
// and/or modify it under the terms of the GNU Lesser General |
// Public License as published by the Free Software Foundation; |
// either version 2.1 of the License, or (at your option) any |
// later version. |
// |
// This source is distributed in the hope that it will be |
// useful, but WITHOUT ANY WARRANTY; without even the implied |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
// PURPOSE. See the GNU Lesser General Public License for more |
// details. |
// |
// You should have received a copy of the GNU Lesser General |
// Public License along with this source; if not, download it |
// from http://www.opencores.org/lgpl.shtml |
////////////////////////////////////////////////////////////////////////////////// |
`include "defines.v" |
|
module zero_check ( |
input rst, |
input bp, |
input d0, d1_dx, |
input wu, |
input acc_no_zero, |
|
output acc_no_zero_test, acc_zero_test |
); |
|
reg no_zero_latch, no_zero_check_latch; |
assign acc_no_zero_test = no_zero_latch & no_zero_check_latch; |
assign acc_zero_test = ~no_zero_latch & ~no_zero_check_latch; |
|
always @(posedge bp) |
if (rst) begin |
no_zero_latch <= 0; |
no_zero_check_latch <= 0; |
end else if (wu & d0) begin |
no_zero_latch <= 0; |
no_zero_check_latch <= 0; |
end else if (acc_no_zero & d1_dx) begin |
no_zero_latch <= 1; |
no_zero_check_latch <= 1; |
end; |
|
endmodule |
zero_check.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: decode_ctl.v
===================================================================
--- decode_ctl.v (nonexistent)
+++ decode_ctl.v (revision 23)
@@ -0,0 +1,244 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// IBM 650 Reconstruction in Verilog (i650)
+//
+// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
+// http:////www.opencores.org/project,i650
+//
+// Description: Instruction decode and control.
+//
+// Additional Comments: See US 2959351, Fig. 78.
+//
+// Copyright (c) 2015 Robert Abeles
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, download it
+// from http://www.opencores.org/lgpl.shtml
+//////////////////////////////////////////////////////////////////////////////////
+`include "defines.v"
+
+module decode_ctl (
+ input rst,
+ input ap, bp, cp,
+ input dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
+ input d5_d10, d10_d1_d5, dxl, dxu, d10u,
+ input [0:6] opreg_t, opreg_u, addr_u,
+ input [0:6] ontime_dist,
+ input man_ro_storage, dist_back_sig, d_control, ena_arith_codes,
+ input pgm_stop_sw,
+ input acc_zero_test, acc_no_zero_test, acc_plus_test, acc_minus_test,
+ input single_intlk, arith_restart, overflow_sense_sig, man_acc_reset,
+
+ output all_restarts, use_d_for_i, turn_on_single_intlk, turn_on_op_intlk,
+ output stop_code, code_69, tlu_sig,
+ output mult_sig, divide_sig, reset_sig, no_reset_sig, abs_sig, no_abs_sig,
+ output lower_sig, upper_sig, add_sig, subt_sig,
+ output right_shift_sig, left_shift_sig, half_correct_sig, shift_count_sig,
+ output reg overflow_sense_latch
+ );
+
+ //-----------------------------------------------------------------------------
+ // Miscellaneous signals
+ //-----------------------------------------------------------------------------
+ wire code_90_d_for_i_sig, code_90_restart_sig, code_69_restart_sig,
+ code_00_01_restart_sig, code_30_35_restart, shift_restart,
+ branch_restart, branch_d_for_i, code_47_d_for_i_sig;
+
+ assign all_restarts = code_90_restart_sig | code_69_restart_sig
+ | code_00_01_restart_sig | code_30_35_restart
+ | shift_restart | branch_restart;
+ assign use_d_for_i = code_90_d_for_i_sig | branch_d_for_i
+ | code_47_d_for_i_sig;
+ assign turn_on_single_intlk = end_shift_control;
+
+ //-----------------------------------------------------------------------------
+ // 00 -- No Operation
+ // 01 -- Stop
+ //-----------------------------------------------------------------------------
+ wire code_00_to_04_dctl_p = opreg_t[`biq_b0] & opreg_t[`biq_q0]
+ & opreg_u[`biq_b0] & d_control;
+ wire code_00_dctl_p = code_00_to_04_dctl_p & opreg_u[`biq_q0];
+ wire code_01_dctl_p = code_00_to_04_dctl_p & opreg_u[`biq_q1];
+ wire code_00_01_restart_p = code_00_dctl_p | code_01_dctl_p;
+ digit_pulse c00_rstrt (rst, ap, code_00_01_restart_p,
+ 1'b0, code_00_01_restart_sig);
+ assign stop_code = pgm_stop_sw & code_01_dctl_p;
+
+ //-----------------------------------------------------------------------------
+ // 14 -- Divide
+ // 64 -- Divide and Reset Upper
+ //-----------------------------------------------------------------------------
+ wire code_14_64_dx_d0_p = (dx | d0) & opreg_t[`biq_q1] // schematic missing term
+ & opreg_u[`biq_b0] & opreg_u[`biq_q4];
+ assign divide_sig = (code_14_64_dx_d0_p & ena_arith_codes & opreg_t[`biq_b5])
+ | (code_14_64_dx_d0_p & ena_arith_codes & opreg_t[`biq_b0]);
+
+ //-----------------------------------------------------------------------------
+ // 19 -- Multiply
+ //-----------------------------------------------------------------------------
+ assign mult_sig = (dx | d0) & ena_arith_codes
+ & code_19_or_69_dctl_p & opreg_t[`biq_b0];
+
+ //-----------------------------------------------------------------------------
+ // 30 -- Shift Right
+ // 31 -- Shift and Round
+ // 35 -- Shift Left
+ // 36 -- Shift Left and Count
+ //-----------------------------------------------------------------------------
+ reg shift_control_latch;
+ wire end_shift_control;
+ digit_pulse end_shift (rst, cp, ~shift_control_latch, 1'b1, end_shift_control);
+ wire shift_control_on_p = d_control & d10u & ~single_intlk & opreg_t[`biq_b0]
+ & opreg_t[`biq_q3];
+ always @(posedge ap)
+ if (rst) begin
+ shift_control_latch <= 0;
+ end else if (dxu) begin
+ shift_control_latch <= 0;
+ end else if (shift_control_on_p) begin
+ shift_control_latch <= 1;
+ end;
+
+ wire zero_shift_number = addr_u[`biq_b0] & addr_u[`biq_q0];
+ wire edxl_shift_control = shift_control_latch & dxl;
+ wire code_x5 = opreg_u[`biq_b5] & opreg_u[`biq_q0];
+ wire code_x0 = opreg_u[`biq_b0] & opreg_u[`biq_q0];
+ wire code_x0_or_x5 = code_x0 | code_x5;
+ // turn_on_op_intlk: No zero shift num on 30 or 35 codes
+ assign turn_on_op_intlk = ~(zero_shift_number & shift_control_latch
+ & code_x0_or_x5)
+ & edxl_shift_control;
+ assign code_30_35_restart = zero_shift_number & edxl_shift_control
+ & (code_x0_or_x5);
+
+ assign right_shift_sig = ~zero_shift_number & edxl_shift_control & code_x0;
+ assign left_shift_sig = ~zero_shift_number & edxl_shift_control & code_x5;
+ assign half_correct_sig = shift_control_latch & opreg_u[`biq_b0]
+ & opreg_u[`biq_q1];
+ assign shift_count_sig = shift_control_latch & opreg_u[`biq_b5]
+ & opreg_u[`biq_q1];
+ assign shift_restart = arith_restart & opreg_t[`biq_q3];
+
+ //-----------------------------------------------------------------------------
+ // 44 -- Branch on non-zero upper acc
+ // 45 -- Branch on zero acc
+ // 46 -- Branch on minus acc
+ // 47 -- Branch on adder overflow
+ //-----------------------------------------------------------------------------
+ wire code_44_dctl_edxl_p = d_control & dxl
+ & opreg_t[`biq_b0] & opreg_t[`biq_q4]
+ & opreg_u[`biq_b0] & opreg_u[`biq_q4];
+ wire code_45_to_49_dctl_p = d_control & opreg_t[`biq_b0] & opreg_t[`biq_q4]
+ & opreg_u[`biq_b5];
+ wire code_45_dctl_edxu_p = dxu & code_45_to_49_dctl_p & opreg_u[`biq_q0];
+ wire code_46_dctl_p = code_45_to_49_dctl_p & opreg_u[`biq_q1];
+ wire code_47_dctl_p = code_45_to_49_dctl_p & opreg_u[`biq_q2];
+
+ wire code_44_or_45_restart_p = (code_44_dctl_edxl_p | code_45_dctl_edxu_p)
+ & acc_zero_test;
+ wire code_44_or_45_d_for_i_p = (code_44_dctl_edxl_p | code_45_dctl_edxu_p)
+ & acc_no_zero_test;
+ wire code_46_restart_p = code_46_dctl_p & acc_plus_test;
+ wire code_46_d_for_i_p = code_46_dctl_p & acc_minus_test;
+ wire code_47_restart_p = code_47_dctl_p & d5 & ~overflow_sense_latch;
+
+ wire branch_restart_p = code_44_or_45_restart_p | code_46_restart_p
+ | code_47_restart_p;
+ digit_pulse br_rstrt (rst, bp, branch_restart_p, 1'b0, branch_restart);
+ wire branch_d_for_i_p = code_44_or_45_d_for_i_p | code_46_d_for_i_p;
+ digit_pulse br_d4i (rst, bp, branch_d_for_i_p, 1'b0, branch_d_for_i);
+
+ wire overflow_sense_off_p = man_acc_reset | (code_47_dctl_p & d1);
+ always @(posedge ap) begin
+ if (rst) overflow_sense_latch <= 0;
+ else if (overflow_sense_off_p) overflow_sense_latch <= 0;
+ else if (overflow_sense_sig) overflow_sense_latch <= 1;
+ end;
+ digit_pulse c47_d4i (rst, bp, ~overflow_sense_latch, 1'b1, code_47_d_for_i_sig);
+
+ //-----------------------------------------------------------------------------
+ // 69 -- Load Distributor
+ //-----------------------------------------------------------------------------
+ wire code_19_or_69_dctl_p = opreg_t[`biq_q1] & opreg_u[`biq_b5]
+ & opreg_u[`biq_q4] & d_control;
+ assign code_69 = (code_19_or_69_dctl_p & opreg_t[`biq_b5]) | man_ro_storage;
+ wire code_69_restart_p = code_69 & dist_back_sig;
+ digit_pulse c69_rstrt (rst, ap, code_69_restart_p, 1'b0, code_69_restart_sig);
+
+ //-----------------------------------------------------------------------------
+ // 70 -- Read
+ // 71 -- Punch
+ //-----------------------------------------------------------------------------
+
+
+ //-----------------------------------------------------------------------------
+ // 84 -- Table Lookup
+ //-----------------------------------------------------------------------------
+ assign tlu_sig = d_control & ~single_intlk
+ & opreg_t[`biq_b5] & opreg_t[`biq_q3]
+ & opreg_u[`biq_b0] & opreg_u[`biq_q4];
+
+ //-----------------------------------------------------------------------------
+ // 9x -- Branch on Distributor Digit
+ //-----------------------------------------------------------------------------
+ wire code_9x_dctl_p = opreg_t[`biq_b5] & opreg_t[`biq_q4] & d_control;
+ wire code_90_ctrl = (d5_d10 & code_9x_dctl_p & opreg_u[`biq_b5])
+ | (d10_d1_d5 & code_9x_dctl_p & opreg_u[`biq_b0]);
+ wire code_90_95_p = (d10 | d5) & opreg_u[`biq_q0] & code_90_ctrl;
+ wire code_91_96_p = (d1 | d6) & opreg_u[`biq_q1] & code_90_ctrl;
+ wire code_92_97_p = (d2 | d7) & opreg_u[`biq_q2] & code_90_ctrl;
+ wire code_93_98_p = (d3 | d8) & opreg_u[`biq_q3] & code_90_ctrl;
+ wire code_94_99_p = (d4 | d9) & opreg_u[`biq_q4] & code_90_ctrl;
+ wire code_90_to_99_p = code_90_95_p | code_91_96_p | code_92_97_p
+ | code_93_98_p | code_94_99_p;
+ wire code_90_d_for_i_p = code_90_to_99_p & ontime_dist[`biq_b5]
+ & ontime_dist[`biq_q3];
+ wire code_90_restart_p = code_90_to_99_p & ontime_dist[`biq_b5]
+ & ontime_dist[`biq_q4];
+ digit_pulse c90_d4i (rst, cp, code_90_d_for_i_p, 1'b0, code_90_d_for_i_sig);
+ digit_pulse c90_rstrt (rst, cp, code_90_restart_p, 1'b0, code_90_restart_sig);
+
+ //-----------------------------------------------------------------------------
+ // 10's and 60's Opcode Derived Control Signals
+ //
+ // SIGNAL OPCODES
+ // ------------ ----------------------------------------------
+ // reset_sig 60, 61, 64, 65, 66, 67, 68
+ // no_reset_sig 10, 11, 14, 15, 16, 17, 18, 19, 69
+ // abs_sig 17, 18, 67, 68
+ // no_abs_sig 10, 11, 14, 15, 16, 19, 60, 61, 64, 65, 66, 69
+ // lower_sig 15, 16, 17, 18, 65, 66, 67, 68
+ // upper_sig 10, 11, 14, 60, 61, 64
+ // add_sig 10, 15, 17, 60, 65, 67
+ // subt_sig 11, 16, 18, 61, 66, 68
+ //-----------------------------------------------------------------------------
+ assign reset_sig = ~code_19_or_69_dctl_p & d_control & opreg_t[`biq_b5]
+ & opreg_t[`biq_q1];
+ assign no_reset_sig = code_19_or_69_dctl_p | (d_control & opreg_t[`biq_b0]
+ & opreg_t[`biq_q1]);
+ assign abs_sig = d_control & opreg_t[`biq_q1] & opreg_u[`biq_b5]
+ & (opreg_u[`biq_q2] | opreg_u[`biq_q3]);
+ assign no_abs_sig = d_control & opreg_t[`biq_q1]
+ & (opreg_u[`biq_q4] | opreg_u[`biq_q1]
+ | opreg_u[`biq_q0]);
+ assign lower_sig = ena_arith_codes & dx & ~code_19_or_69_dctl_p
+ & opreg_u[`biq_b5];
+ assign upper_sig = ena_arith_codes & dx & opreg_u[`biq_b0];
+ assign add_sig = ena_arith_codes & (dx | d0)
+ & (opreg_u[`biq_q2] | opreg_u[`biq_q0]);
+ assign subt_sig = ena_arith_codes & (dx | d0)
+ & (opreg_u[`biq_q3] | opreg_u[`biq_q1]);
+
+endmodule
decode_ctl.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: operator_ctl.v
===================================================================
--- operator_ctl.v (revision 22)
+++ operator_ctl.v (revision 23)
@@ -49,7 +49,7 @@
output reg read_gs, write_gs,
output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
output run_control, half_or_pgm_stop, ri_storage, ro_storage,
- storage_control,
+ storage_control, err_restart_sw, ovflw_stop_sw, ovflw_sense_sw,
output reg man_pgm_reset, man_acc_reset, hard_reset,
output set_8000, reset_8000,
@@ -80,6 +80,9 @@
: `biq_blank;
assign set_8000 = man_pgm_reset & (ctl_sw_addr_stop | ctl_sw_run);
assign reset_8000 = man_pgm_reset & ctl_sw_manual;
+ assign err_restart_sw = err_sw_sense;
+ assign ovflw_stop_sw = ovflw_sw_stop;
+ assign ovflw_sense_sw = ovflw_sw_sense;
//-----------------------------------------------------------------------------
// Calculate the RAM address of the general storage word at address gs_addr_.
/error_stop.v
0,0 → 1,124
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// IBM 650 Reconstruction in Verilog (i650) |
// |
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project |
// http:////www.opencores.org/project,i650 |
// |
// Description: Error stop and sense controls. |
// |
// Additional Comments: See US 2959351, Fig. 79. |
// |
// Copyright (c) 2015 Robert Abeles |
// |
// This source file is free software; you can redistribute it |
// and/or modify it under the terms of the GNU Lesser General |
// Public License as published by the Free Software Foundation; |
// either version 2.1 of the License, or (at your option) any |
// later version. |
// |
// This source is distributed in the hope that it will be |
// useful, but WITHOUT ANY WARRANTY; without even the implied |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
// PURPOSE. See the GNU Lesser General Public License for more |
// details. |
// |
// You should have received a copy of the GNU Lesser General |
// Public License along with this source; if not, download it |
// from http://www.opencores.org/lgpl.shtml |
////////////////////////////////////////////////////////////////////////////////// |
`include "defines.v" |
|
module error_stop ( |
input rst, |
input ap, dp, |
input dxu, d10, wl, |
input err_restart_sw, err_reset, err_sense_reset, clock_err_sig, |
err_stop_sig, restart_reset_busy, |
|
output err_sense_light, |
output reg err_stop_ed0u, err_sense_restart, restart_reset |
); |
|
reg err_stop, err_sense; |
|
//----------------------------------------------------------------------------- |
// The err_sense flip-flop does nothing but control a light. |
//----------------------------------------------------------------------------- |
assign err_sense_light = err_sense; |
always @(posedge ap) |
if (rst) err_sense <= 0; |
else if (err_sense_reset) err_sense <= 0; |
else if (err_stop & err_restart_sw) err_sense <= 1; |
|
//----------------------------------------------------------------------------- |
// This FSM controls the error stop / error restart process. |
//----------------------------------------------------------------------------- |
reg [0:2] state; |
`define restart_idle 3'd0 |
`define restart_1 3'd1 |
`define restart_2 3'd2 |
`define restart_3 3'd3 |
`define restart_4 3'd4 |
`define restart_5 3'd5 |
`define restart_6 3'd6 |
always @(posedge dp) |
if (rst) begin |
err_sense_restart <= 0; |
restart_reset <= 0; |
err_stop <= 0; |
err_stop_ed0u <= 0; |
state <= `restart_idle; |
end else |
case (state) |
`restart_idle: // start state, transition on external err signal |
// error restart switch selects next state |
if (err_reset) |
err_stop <= 0; |
else if (~err_stop & (clock_err_sig | err_stop_sig)) begin |
err_stop <= 1; |
if (err_restart_sw) |
state <= `restart_1; |
else |
state <= `restart_5; |
end |
`restart_1: // >>>error_sense switch position<<< |
// wait for dxu |
// signal console to begin restart reset |
// turn off run latch |
if (dxu) begin |
restart_reset <= 1; |
err_stop_ed0u <= 1; |
state <= `restart_2; |
end |
`restart_2: begin // wait for restart reset to start |
err_stop_ed0u <= 0; |
if (restart_reset_busy) begin |
restart_reset <= 0; |
state <= `restart_3; |
end |
end |
`restart_3: // wait for end of restart reset |
// turn on run latch |
if (~restart_reset_busy & wl & d10) begin |
err_sense_restart <= 1; |
err_stop <= 0; |
state <= `restart_4; |
end |
`restart_4: begin |
err_sense_restart <= 0; |
state <= `restart_idle; |
end |
`restart_5: // >>>error_stop switch position<<< |
// turn off run latch |
if (dxu) begin |
err_stop_ed0u <= 1; |
state <= `restart_6; |
end |
`restart_6: begin |
err_stop_ed0u <= 0; |
state <= `restart_idle; |
end |
endcase; |
|
endmodule |
error_stop.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: check_acc_tlu.v
===================================================================
--- check_acc_tlu.v (nonexistent)
+++ check_acc_tlu.v (revision 23)
@@ -0,0 +1,72 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// IBM 650 Reconstruction in Verilog (i650)
+//
+// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
+// http:////www.opencores.org/project,i650
+//
+// Description: Error check accumulator, adder carry, and TLU.
+//
+// Additional Comments: See US 2959351, Fig. 83.
+//
+// Copyright (c) 2015 Robert Abeles
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, download it
+// from http://www.opencores.org/lgpl.shtml
+//////////////////////////////////////////////////////////////////////////////////
+`include "defines.v"
+
+module check_acc_tlu (
+ input rst,
+ input ap, bp,
+ input d0, d2, d1_dx,
+ input [0:6] acc_ped_out,
+ input sel_store_add_gate, err_reset, carry_test_latch, no_carry_test_latch,
+
+ output acc_zero, acc_no_zero,
+ output reg check_latch
+ );
+
+ reg tlu_check;
+ assign acc_zero = acc_ped_out[`biq_b0] & acc_ped_out[`biq_q0];
+ assign acc_no_zero = acc_ped_out[`biq_b5] | acc_ped_out[`biq_q4]
+ | acc_ped_out[`biq_q3] | acc_ped_out[`biq_q2]
+ | acc_ped_out[`biq_q1];
+ wire acc_err1_p = ~(acc_zero | acc_no_zero) & d1_dx;
+ wire acc_err2_p = (acc_zero & acc_no_zero) & d1_dx;
+ wire carry_err1_p = ~(carry_test_latch | no_carry_test_latch) & tlu_check;
+ wire carry_err2_p = carry_test_latch & no_carry_test_latch;
+ wire set_check_latch_p = acc_err1_p | acc_err2_p | carry_err1_p | carry_err2_p;
+
+ always @(posedge ap)
+ if (rst) begin
+ tlu_check <= 0;
+ end else if (d0) begin
+ tlu_check <= 0;
+ end else if (d2 & sel_store_add_gate) begin
+ tlu_check <= 1;
+ end;
+
+ always @(posedge bp)
+ if (rst) begin
+ check_latch <= 0;
+ end else if (err_reset) begin
+ check_latch <= 0;
+ end else if (set_check_latch_p) begin
+ check_latch <= 1;
+ end;
+
+endmodule
check_acc_tlu.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: toplev.v
===================================================================
--- toplev.v (revision 22)
+++ toplev.v (revision 23)
@@ -7,8 +7,7 @@
//
// Description: Top level.
//
-// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
-// counters provided to address general storage and register RAMs.
+// Additional Comments:
//
// Copyright (c) 2015 Robert Abeles
//
@@ -139,6 +138,27 @@
ar_addr_8002, ar_addr_8003, ar_addr_8002_8003, ar_invalid_addr;
//-----------------------------------------------------------------------------
+ // Accumulator and TLU validity checking
+ //-----------------------------------------------------------------------------
+ wire ca_acc_zero, ca_acc_no_zero, ca_check_latch;
+
+ //-----------------------------------------------------------------------------
+ // Register validity checking
+ //-----------------------------------------------------------------------------
+ wire ck_error_stop, ck_acc_check_light, ck_prog_check_light,
+ ck_dist_check_light;
+
+ //-----------------------------------------------------------------------------
+ // Decode control
+ //-----------------------------------------------------------------------------
+ wire dc_all_restarts, dc_use_d_for_i, dc_turn_on_single_intlk,
+ dc_turn_on_op_intlk, dc_stop_code, dc_code_69, dc_tlu_sig, dc_mult_sig,
+ dc_divide_sig, dc_reset_sig, dc_no_reset_sig, dc_abs_sig, dc_no_abs_sig,
+ dc_lower_sig, dc_upper_sig, dc_add_sig, dc_subt_sig, dc_right_shift_sig,
+ dc_left_shift_sig, dc_half_correct_sig, dc_shift_count_sig,
+ dc_overflow_sense_latch;
+
+ //-----------------------------------------------------------------------------
// Distributor
//-----------------------------------------------------------------------------
wire [0:6] ds_early_out, ds_ontime_out;
@@ -145,10 +165,10 @@
wire ds_back_sig;
//-----------------------------------------------------------------------------
- // Register validity checking
+ // Error stop
//-----------------------------------------------------------------------------
- wire ck_error_stop, ck_acc_check_light, ck_prog_check_light,
- ck_dist_check_light;
+ wire es_err_sense_light, es_err_stop_ed0u, es_err_sense_restart,
+ es_restart_reset;
//-----------------------------------------------------------------------------
// General storage
@@ -171,7 +191,8 @@
wire oc_read_gs, oc_write_gs;
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
- oc_storage_control;
+ oc_storage_control, oc_err_restart_sw, oc_ovflw_stop_sw,
+ oc_ovflw_sense_sw;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
oc_hard_reset;
wire oc_restart_reset_busy;
@@ -194,6 +215,11 @@
wire tr_gs_write;
wire [0:4] tr_gs_in;
wire [0:6] tr_gs_out;
+
+ //-----------------------------------------------------------------------------
+ // Accumulator zero check
+ //-----------------------------------------------------------------------------
+ wire zc_acc_no_zero_test, zc_acc_zero_test;
add_in_a aa (
.acc_early_out(ac_early_out),
@@ -201,12 +227,12 @@
.prog_step_early_out(ps_early_out),
.select_storage_out(ss_selected_out),
.addr_u(ar_addr_u),
- .acc_true_add_gate(1'b0),
- .acc_compl_add_gate(1'b0),
- .left_shift_gate(1'b0),
- .prog_step_add_gate(1'b0),
- .shift_num_gate(1'b0),
- .select_stor_add_gate(1'b0),
+ .acc_true_add_gate(1'b0), //
+ .acc_compl_add_gate(1'b0), //
+ .left_shift_gate(1'b0), //
+ .prog_step_add_gate(1'b0), //
+ .shift_num_gate(1'b0), //
+ .select_stor_add_gate(1'b0), //
.adder_entry_a(aa_entry_a)
);
@@ -213,13 +239,13 @@
add_in_b ab (
.dist_early_out(ds_early_out),
.dist_ontime_out(ds_ontime_out),
- .special_int_entry(10'd0),
- .ontime_dist_add_gate_tlu(1'b0),
- .dist_compl_add_gate(1'b0),
- .upper_lower_check(1'b0),
- .dist_blank_gate(1'b0),
- .early_dist_zero_entry(1'b0),
- .dist_true_add_gate(1'b0),
+ .special_int_entry(10'd0), //
+ .ontime_dist_add_gate_tlu(1'b0), //
+ .dist_compl_add_gate(1'b0), //
+ .upper_lower_check(1'b0), //
+ .dist_blank_gate(1'b0), //
+ .early_dist_zero_entry(1'b0), //
+ .dist_true_add_gate(1'b0), //
.adder_entry_b(ab_entry_b)
);
@@ -238,13 +264,13 @@
.wl(wl),
.adder_out(ad_adder_out),
.console_out(oc_console_out),
- .acc_regen_gate(1'b1),
- .right_shift_gate(1'b0),
- .acc_ri_gate(1'b0),
+ .acc_regen_gate(1'b1), //
+ .right_shift_gate(1'b0), //
+ .acc_ri_gate(1'b0), //
.acc_ri_console(oc_acc_ri_console),
- .zero_shift_count(1'b0),
+ .zero_shift_count(1'b0), //
.man_acc_reset(oc_man_acc_reset),
- .reset_op(1'b0),
+ .reset_op(1'b0), //
.early_idx(early_idx),
.ontime_idx(ontime_idx),
.early_out(ac_early_out),
@@ -253,7 +279,7 @@
);
adder ad (
- .rst(rst),
+ .rst(oc_hard_reset),
.ap(ap),
.bp(bp),
.dp(dp),
@@ -267,22 +293,22 @@
.wl(wl),
.entry_a(aa_entry_a),
.entry_b(ab_entry_b),
- .tlu_on(1'b0),
- .left_shift_off(1'b1),
- .left_shift_on(1'b0),
- .no_carry_insert(1'b0),
- .no_carry_blank(1'b0),
- .carry_insert(1'b0),
- .carry_blank(1'b0),
- .zero_insert(1'b0),
+ .tlu_on(1'b0), //
+ .left_shift_off(1'b1), //
+ .left_shift_on(1'b0), //
+ .no_carry_insert(1'b0), //
+ .no_carry_blank(1'b0), //
+ .carry_insert(1'b0), //
+ .carry_blank(1'b0), //
+ .zero_insert(1'b0), //
.error_reset(oc_err_reset),
- .quotient_digit_on(1'b0),
- .overflow_stop_sw(1'b1), // missing from oc_
- .overflow_sense_sw(1'b0), // ditto
- .mult_div_off(1'b0),
- .dist_true_add_gate(1'b0),
- .acc_true_add_latch(1'b0),
- .shift_overflow(1'b0),
+ .quotient_digit_on(1'b0), //
+ .overflow_stop_sw(oc_ovflw_stop_sw),
+ .overflow_sense_sw(oc_ovflw_sense_sw),
+ .mult_div_off(1'b0), //
+ .dist_true_add_gate(1'b0), //
+ .acc_true_add_latch(1'b0), //
+ .shift_overflow(1'b0), //
.adder_out(ad_adder_out),
.carry_test(ad_carry_test),
.no_carry_test(ad_no_carry_test),
@@ -293,7 +319,7 @@
);
addr_reg ar (
- .rst(rst),
+ .rst(oc_hard_reset),
.ap(ap),
.bp(bp),
.dx(dx),
@@ -322,14 +348,14 @@
.s3(s3),
.s4(s4),
.error_reset(oc_err_reset),
- .restart_a(1'b0),
+ .restart_a(1'b0), //
.set_8000(oc_set_8000),
.reset_8000(oc_reset_8000),
- .tlu_band_change(1'b0),
+ .tlu_band_change(1'b0), //
.double_write(gs_double_write),
.no_write(gs_no_write),
- .bs_to_gs(1'b0),
- .ri_gs(1'b0),
+ .bs_to_gs(1'b0), //
+ .ri_gs(1'b0), //
.ps_reg_in(ps_ontime_out),
.console_in(oc_addr_out),
.ri_addr_reg(op_ri_addr_reg),
@@ -348,6 +374,23 @@
.invalid_addr(ar_invalid_addr)
);
+ check_acc_tlu ca (
+ .rst(oc_hard_reset),
+ .ap(ap),
+ .bp(bp),
+ .d0(d0),
+ .d2(d2),
+ .d1_dx(d1_dx),
+ .acc_ped_out(ac_ped_out),
+ .sel_store_add_gate(1'b0), //
+ .err_reset(oc_err_reset),
+ .carry_test_latch(ad_carry_test),
+ .no_carry_test_latch(ad_no_carry_test),
+ .acc_zero(ca_acc_zero),
+ .acc_no_zero(ca_acc_no_zero),
+ .check_latch(ca_check_latch)
+ );
+
checking ck (
.rst(oc_hard_reset),
.bp(bp),
@@ -356,12 +399,74 @@
.prog_ontime(ps_ontime_out),
.dist_ontime(ds_ontime_out),
.error_reset(oc_err_reset),
- .tlu_or_zero_check(1'b0),
+ .tlu_or_zero_check(ca_check_latch),
.error_stop(ck_error_stop),
.acc_check_light(ck_acc_check_light),
.prog_check_light(ck_prog_check_light),
.dist_check_light(ck_dist_check_light)
);
+decode_ctl dc (
+ .rst(oc_hard_reset),
+ .ap(ap),
+ .bp(bp),
+ .cp(cp),
+ .dx(dx),
+ .d0(d0),
+ .d1(d1),
+ .d2(d2),
+ .d3(d3),
+ .d4(d4),
+ .d5(d5),
+ .d6(d6),
+ .d7(d7),
+ .d8(d8),
+ .d9(d9),
+ .d10(d10),
+ .d5_d10(d5_d10),
+ .d10_d1_d5(d10_d1_d5),
+ .dxl(dxl),
+ .dxu(dxu),
+ .d10u(d10u),
+ .opreg_t(op_opreg_t),
+ .opreg_u(op_opreg_u),
+ .addr_u(ar_addr_u),
+ .ontime_dist(ds_ontime_out),
+ .man_ro_storage(1'b0), //
+ .dist_back_sig(ds_back_sig),
+ .d_control(1'b0), //
+ .ena_arith_codes(1'b0), //
+ .pgm_stop_sw(pgm_stop_sw), // ***
+ .acc_zero_test(zc_acc_zero_test),
+ .acc_no_zero_test(zc_acc_no_zero_test),
+ .acc_plus_test(1'b0), //
+ .acc_minus_test(1'b0), //
+ .single_intlk(1'b0), //
+ .arith_restart(1'b0), //
+ .overflow_sense_sig(ad_overflow_sense_sig),
+ .man_acc_reset(oc_man_acc_reset),
+ .all_restarts(dc_all_restarts),
+ .use_d_for_i(dc_use_d_for_i),
+ .turn_on_single_intlk(dc_turn_on_single_intlk),
+ .turn_on_op_intlk(dc_turn_on_op_intlk),
+ .stop_code(dc_stop_code),
+ .code_69(dc_code_69),
+ .tlu_sig(dc_tlu_sig),
+ .mult_sig(dc_mult_sig),
+ .divide_sig(dc_divide_sig),
+ .reset_sig(dc_reset_sig),
+ .no_reset_sig(dc_no_reset_sig),
+ .abs_sig(dc_abs_sig),
+ .no_abs_sig(dc_no_abs_sig),
+ .lower_sig(dc_lower_sig),
+ .upper_sig(dc_upper_sig),
+ .add_sig(dc_add_sig),
+ .subt_sig(dc_subt_sig),
+ .right_shift_sig(dc_right_shift_sig),
+ .left_shift_sig(dc_left_shift_sig),
+ .half_correct_sig(dc_half_correct_sig),
+ .shift_count_sig(dc_shift_count_sig),
+ .overflow_sense_latch(dc_overflow_sense_latch)
+ );
distributor ds (
.rst(oc_hard_reset),
@@ -372,11 +477,11 @@
.d0(d0),
.d10(d10),
.selected_storage(ss_selected_out),
- .ri_dist(1'd0),
+ .ri_dist(1'd0), //
.acc_ontime(ac_ontime_out),
- .start_acc_dist_ri(1'd0),
+ .start_acc_dist_ri(1'd0), //
.end_acc_dist_ri(1'd0),
- .acc_dist_ri(1'd0),
+ .acc_dist_ri(1'd0), //
.man_acc_reset(oc_man_acc_reset),
.early_idx(early_idx),
.ontime_idx(ontime_idx),
@@ -385,6 +490,25 @@
.dist_back_sig(ds_back_sig)
);
+ error_stop es (
+ .rst(oc_hard_reset),
+ .ap(ap),
+ .dp(dp),
+ .dxu(dxu),
+ .d10(d10),
+ .wl(wl),
+ .err_restart_sw(oc_err_restart_sw),
+ .err_reset(oc_err_reset),
+ .err_sense_reset(oc_err_sense_reset),
+ .clock_err_sig(1'b0), //
+ .err_stop_sig(ck_error_stop),
+ .restart_reset_busy(oc_restart_reset_busy),
+ .err_sense_light(es_err_sense_light),
+ .err_stop_ed0u(es_err_stop_ed0u),
+ .err_sense_restart(es_err_sense_restart),
+ .restart_reset(es_restart_reset)
+ );
+
gen_store gs (
.rst(oc_hard_reset),
.ap(ap),
@@ -430,7 +554,7 @@
.dist_ontime(ds_ontime_out),
.prog_ontime(ps_ontime_out),
.command(command),
- .restart_reset(1'b0),
+ .restart_reset(es_restart_reset),
.data_out(oc_data_out),
.addr_out(oc_addr_out),
.console_out(oc_console_out),
@@ -449,6 +573,9 @@
.ri_storage(oc_ri_storage),
.ro_storage(oc_ro_storage),
.storage_control(oc_storage_control),
+ .err_restart_sw(oc_err_restart_sw),
+ .ovflw_stop_sw(oc_ovflw_stop_sw),
+ .ovflw_sense_sw(oc_ovflw_sense_sw),
.man_pgm_reset(oc_man_pgm_reset),
.man_acc_reset(oc_man_acc_reset),
.set_8000(oc_set_8000),
@@ -471,11 +598,11 @@
.d10(d10),
.d1_d5(d1_d5),
.d5_dx(d5_dx),
- .restart_a(1'b0),
- .restart_b(1'b0),
- .d_alt(1'b0),
- .i_alt(1'b0),
- .tlu_band_change(1'b0),
+ .restart_a(1'b0), //
+ .restart_b(1'b0), //
+ .d_alt(1'b0), //
+ .i_alt(1'b0), //
+ .tlu_band_change(1'b0), //
.man_prog_reset(oc_man_pgm_reset),
.prog_step_ped(ps_ped_out),
.opreg_t(op_opreg_t),
@@ -493,11 +620,11 @@
.early_idx(early_idx),
.ontime_idx(ontime_idx),
.man_prog_reset(oc_man_pgm_reset),
- .rips(1'b0),
- .adder_out(7'b0),
- .sel_store_out(7'b0),
- .prog_ped_regen(1'b1),
- .prog_add(1'b0),
+ .rips(1'b0), //
+ .adder_out(ad_adder_out),
+ .sel_store_out(ss_selected_out),
+ .prog_ped_regen(1'b1), //
+ .prog_add(1'b0), //
.early_out(ps_early_out),
.ontime_out(ps_ontime_out),
.ped_out(ps_ped_out),
@@ -511,13 +638,13 @@
.addr_8000(ar_addr_8000),
.addr_8001(ar_addr_8001),
.addr_8002_8003(ar_addr_8002_8003),
- .addr_hot_8000(1'b0),
+ .addr_hot_8000(1'b0), //
.acc_ontime(ac_ontime_out),
.dist_ontime(ds_ontime_out),
.gs_out(tr_gs_out),
.console_switches(oc_data_out),
- .acc_plus(1'b0),
- .acc_minus(1'b0),
+ .acc_plus(1'b0), //
+ .acc_minus(1'b0), //
.selected_out(ss_selected_out)
);
@@ -525,8 +652,8 @@
.dist_early_out(`biq_blank),
.bs_out(`biq_blank),
.console_out(oc_console_out),
- .ri_gs(1'b0),
- .ri_bs(1'b0),
+ .ri_gs(1'b0), //
+ .ri_bs(1'b0), //
.ri_console(oc_write_gs),
.n800x(ar_addr_no_800x),
.console_read_gs(oc_read_gs),
@@ -535,5 +662,16 @@
.gs_in(tr_gs_in),
.gs_biq_out(tr_gs_out)
);
+
+ zero_check zc (
+ .rst(oc_hard_reset),
+ .bp(bp),
+ .d0(d0),
+ .d1_dx(d1_dx),
+ .wu(wu),
+ .acc_no_zero(ca_acc_no_zero),
+ .acc_no_zero_test(zc_acc_no_zero_test),
+ .acc_zero_test(zc_acc_zero_test)
+ );
endmodule
\ No newline at end of file