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/ctl_commutator.v
0,0 → 1,372
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Control commutator.
//
// Additional Comments: See US 2959351, Fig. 81.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module ctl_commutator (
input rst,
input ap, bp, cp, dp,
input dx, d1, d3, d7, d9, d10,
input dxu, dxl,
input wu, wl,
input invalid_addr,
input man_prog_reset, run_control_sw, program_start_sw, manual_ri_storage_sw,
input manual_ro_storage_sw, manual_error_reset_sw,
input half_or_pgm_stop,
input prog_restart, error_stop, error_sense_restart, arith_restart,
input stop_code, code_69, start_10s_60s, end_shift_cntrl, tlu_on,
input end_of_operation, turn_on_op_intlk, decode_restarts,
input use_d_for_i, dist_back_signal,
input error_stop_ed0u, divide_overflow_stop,
exceed_address_or_stor_select_light,
input [0:6] opreg_t, opreg_u,
input addr_no_800x, addr_8001,
input dynamic_addr_hit,
output reg restart_a, restart_b,
output reg i_alt, d_alt,
output reg manual_stop_start, run_latch,
output reg enable_ri,
output manual_ri_storage, manual_ro_storage,
output reg manual_start_ri_dist_latch,
output i_control_pulse,
output i_control, d_control, d_control_no_8001,
output reg start_ri,
output reg rips_ri_dist_intlk_a, rips_ri_dist_intlk_b, op_intlk, single_intlk,
output rips, ri_dist,
output reg acc_to_dist_ri_latch,
output start_acc_to_dist_ri, end_acc_to_dist_ri,
output reg rigs,
output end_rigs
);
 
//-----------------------------------------------------------------------------
// Restart control
//-----------------------------------------------------------------------------
wire ri_dist_restart, arith_codes_restart;
assign all_restarts = decode_restarts
| prog_restart
| ri_dist_restart
| arith_codes_restart;
always @(posedge ap)
if (rst) begin
restart_a <= 0;
end else if (~invalid_addr & all_restarts & ~restart_b) begin
restart_a <= 1;
end else if (man_prog_reset | (restart_b & dx)) begin
restart_a <= 0;
end;
always @(posedge ap)
if (rst) begin
restart_b <= 0;
end else if (restart_a & dx) begin
restart_b <= 1;
end else if (restart_b & dx) begin
restart_b <= 0;
end;
//-----------------------------------------------------------------------------
// I / D alternation
//-----------------------------------------------------------------------------
assign run_control = run_control_sw & run_latch;
assign d_control_no_8001 = opreg_t[`biq_q1] & d_control & ~addr_8001;
wire d_control_8001 = opreg_t[`biq_q1] & d_control & addr_8001;
assign i_control = i_alt & ~restart_b & run_latch;
assign d_control = d_alt & ~op_intlk & ~restart_b & run_control;
always @(posedge dp)
if (rst) begin
i_alt <= 0;
d_alt <= 1;
end else if (man_prog_reset | use_d_for_i ) begin
i_alt <= 0;
d_alt <= 1;
end else if (dx & restart_b & run_control) begin
i_alt <= d_alt;
d_alt <= i_alt;
end;
//-----------------------------------------------------------------------------
// 8uS i_control_pulse is emited at the rising edge of (ap & i_control)
//-----------------------------------------------------------------------------
digit_pulse i_ctl (rst, ap, (i_control | manual_ro_storage | d_control_no_8001), 1'b0, i_control_pulse);
//-----------------------------------------------------------------------------
// CPU running control
//-----------------------------------------------------------------------------
assign manual_ri_storage = manual_ri_storage_sw & run_latch;
assign manual_ro_storage = manual_ro_storage_sw & run_latch;
always @(posedge ap)
if (rst) begin
manual_stop_start <= 0;
end else if (dxl) begin
manual_stop_start <= 0;
end else if (program_start_sw & dxu & ~error_stop) begin
manual_stop_start <= 1;
end;
wire turn_off_run_latch = half_or_pgm_stop & ~invalid_addr & all_restarts & ~restart_b;
always @(posedge bp)
if (rst) begin
run_latch <= 0;
end else if ( (manual_ri_storage & end_rigs)
| (manual_ro_storage & dist_back_signal)
| manual_error_reset_sw
| error_stop_ed0u
| divide_overflow_stop
| exceed_address_or_stor_select_light
| stop_code
| turn_off_run_latch ) begin
run_latch <= 0;
end else if (manual_stop_start | error_sense_restart) begin
run_latch <= 1;
end;
 
//-----------------------------------------------------------------------------
// Accumulator to distributor read-in control
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Predicates for accumulator to distributor read-in. Instructions decoded:
// 20 STL Store Lower in Memory
// 21 STU Store Upper in Memory
// 22 STDA Store Lower Data Address
// 23 STIA Store Lower Inst Address
// 24 STD Store Distributor
//-----------------------------------------------------------------------------
assign op_20_24_d_p = opreg_t[`biq_b0] & opreg_t[`biq_q2] & opreg_u[`biq_q0] & d_control;
assign op_20_24_d_intlk_p = op_20_24_d_p & ~single_intlk;
 
assign op_20_d_intlk_d10u_p = op_20_24_d_intlk_p & opreg_u[`biq_q0] & wu & d10;
assign op_21_d_intlk_d10l_p = op_20_24_d_intlk_p & opreg_u[`biq_q1] & wl & d10;
assign op_22_d_intlk_d3l_p = op_20_24_d_intlk_p & opreg_u[`biq_q2] & wl & d3;
assign op_23_d_intlk_dxl_p = op_20_24_d_intlk_p & opreg_u[`biq_q3] & wl & dx;
assign acc_to_dist_ri_on_p = op_20_d_intlk_d10u_p | op_21_d_intlk_d10l_p | op_22_d_intlk_d3l_p | op_23_d_intlk_dxl_p;
assign op_20_d_intlk_d9_p = op_20_24_d_intlk_p & opreg_u[`biq_q0] & d9;
assign op_21_d_intlk_d9u_p = op_20_24_d_intlk_p & opreg_u[`biq_q1] & wu & d9;
assign op_22_d_intlk_d7_p = op_20_24_d_intlk_p & opreg_u[`biq_q2] & d7;
assign op_23_d_intlk_d3_p = op_20_24_d_intlk_p & opreg_u[`biq_q3] & d3;
assign acc_to_dist_ri_off_p = op_20_d_intlk_d9_p | op_21_d_intlk_d9u_p | op_22_d_intlk_d7_p | op_23_d_intlk_d3_p;
 
assign op_24_d_intlk_p = op_20_24_d_intlk_p & opreg_u[`biq_q4];
always @(posedge bp)
if (rst) begin
acc_to_dist_ri_latch <= 0;
end else if (acc_to_dist_ri_off_p) begin
acc_to_dist_ri_latch <= 0;
end else if (acc_to_dist_ri_on_p) begin
acc_to_dist_ri_latch <= 1;
end;
digit_pulse a2d_ri_on (rst, cp, acc_to_dist_ri_latch, 1'b0, start_acc_to_dist_ri);
digit_pulse a2d_ri_off(rst, cp, ~acc_to_dist_ri_latch, 1'b1, end_acc_to_dist_ri);
//-----------------------------------------------------------------------------
// Manual read-in control
//-----------------------------------------------------------------------------
wire man_start_ri_dist_sig;
digit_pulse ri_dist_sig (rst, ap, manual_ri_storage, 1'b0, man_start_ri_dist_sig);
always @(posedge bp)
if (rst) begin
manual_start_ri_dist_latch <= 0;
end
//-----------------------------------------------------------------------------
// Read-in control
//-----------------------------------------------------------------------------
always @(posedge dp)
if (rst) begin
enable_ri <= 0;
end else if (man_prog_reset | start_ri) begin
enable_ri <= 0;
end else if ( start_acc_to_dist_ri
| man_start_ri_dist_sig
| i_control_pulse
| op_24_d_intlk_p ) begin
enable_ri <= 1;
end;
always @(posedge cp)
if (rst) begin
start_ri <= 0;
end else if (d1) begin
start_ri <= 0;
end else if (d9 & addr_no_800x & enable_ri & dynamic_addr_hit) begin
start_ri <= 1;
end;
 
//-----------------------------------------------------------------------------
// Read-in general storage
//-----------------------------------------------------------------------------
always @(posedge bp)
if (rst) begin
rigs <= 0;
end else if (d10 & ~start_ri) begin
rigs <= 0;
end else if ((d10 & manual_ri_storage & start_ri) | (d10 & op_20_24_d_p & start_ri)) begin
rigs <= 1;
end;
digit_pulse end_rigs_sig (rst, cp, ~rigs, 1'b1, end_rigs);
 
//-----------------------------------------------------------------------------
// Read-in distributor
//-----------------------------------------------------------------------------
assign ri_dist = (dx & start_ri & ~rips_ri_dist_intlk_b & (manual_ro_storage | d_control_no_8001)) | man_start_ri_dist_sig;
assign ri_dist_restart = dist_back_sig_latch & end_rigs;
reg dist_back_sig_latch;
always @(posedge bp)
if (rst) begin
dist_back_sig_latch <= 0;
end else if (man_prog_reset | dist_back_signal) begin
dist_back_sig_latch <= 1;
end else if (ri_dist | start_acc_to_dist_ri) begin
dist_back_sig_latch <= 0;
end;
//-----------------------------------------------------------------------------
// Read-in program step
//-----------------------------------------------------------------------------
assign rips = dx & start_ri & i_control & ~rips_ri_dist_intlk_b;
//-----------------------------------------------------------------------------
// Enable arithmetic codes latch
//-----------------------------------------------------------------------------
reg enable_arith_codes_latch;
wire d_control_8001_sig;
digit_pulse ac_on_sig (rst, ap, d_control_8001, 1'b0, d_control_8001_sig);
always @(posedge bp)
if (rst) begin
enable_arith_codes_latch <= 0;
end else if ((arith_restart & dist_back_sig_latch) | code_69) begin
enable_arith_codes_latch <= 0;
end else if (d_control_8001_sig | (d_control_no_8001 & dist_back_signal)) begin
enable_arith_codes_latch <= 1;
end;
 
digit_pulse ac_restart (rst, cp, ~arith_restart, 1'b1, arith_codes_restart);
//-----------------------------------------------------------------------------
// Interlocks
//-----------------------------------------------------------------------------
 
// RIPS-RID interlock A and B latches: These latches provide an interlock to
// insure that only one RIPS or storage to distributor RI signal will be
// developed on any commutator half cycle. Interlock B must be off to obtain
// either RIPS or storage to distributor RI. Either signal when developed
// turns on interlock A which turns off with the next D1 and turns interlock
// B on. With interlock B on, one of the conditions necessary for RIPS or
// storage to distributor RI is removed. Interlock B is reset by any restart,
// program reset, or manual RI.
always @(posedge bp)
if (rst) begin
rips_ri_dist_intlk_a <= 0;
rips_ri_dist_intlk_b <= 0;
end else begin
if (d1) begin
rips_ri_dist_intlk_a <= 0;
end else if (ri_dist | rips) begin
rips_ri_dist_intlk_a <= 1;
end
if (all_restarts | man_prog_reset) begin
rips_ri_dist_intlk_b <= 0;
end else if (d1 & rips_ri_dist_intlk_a) begin
rips_ri_dist_intlk_b <= 1;
end
end;
 
// Operation interlock latch (791, Fig 81i): The off output of this latch is
// one of the conditions needed for the development of the "D" control signal
// and for the turning of the start RI latch on an 800X address. The arith-
// metic and shift operations make use of the accumulator and distributor and
// may require several word times for their completion. The restart signal on
// these operations is developed during the first operation word interval.
// Thus the commutator can advance concurrently with the performance of the
// operation and allow the next instruction to be located, read into program
// step storage, restart to "D" and transfer the new Op. code and "D" address
// to the registers. At this point further advance of the commutator cannot
// be allowed until the preceeding operation is completed. This interlocking
// is done by allowing arithmetic and shift signals to turn on the operation
// interlock latch, removing one of the necessary conditions for "D" control.
// When an arithmetic or shift instruction has an 800X "I" address, the
// location of the next instruction must be prevented until the preceeding
// operation is complete, since the instruction itself is in the process of
// being developed by the operation. This is accomplished by the Op.
// interlock off condition necessary for turning on the start RI.
wire set_op_intlk_sig;
wire set_op_intlk_p = wl & opreg_t[`biq_q1] & enable_arith_codes_latch & ~single_intlk;
digit_pulse op_ilk_sig (rst, ap, ~set_op_intlk_p, 1'b1, set_op_intlk_sig);
always @(posedge bp)
if (rst) begin
op_intlk <= 0;
end else if (man_prog_reset | end_of_operation) begin
op_intlk <= 0;
end else if (set_op_intlk_sig | turn_on_op_intlk) begin
op_intlk <= 1;
end;
 
// Single interlock latch (857, Fig 81i): This latch when off, conditions
// the development of arithmetic code signals, store code signals, shift
// code signals and TLU signals. When any of these signals are developed
// they cause the single interlock latch to be turned on thus preventing
// further development of the same signals during successive word intervals
// of the same commutator half cycle. The latch is turned off by any
// restart or by program reset.
wire single_intlk_set_p = (enable_ri & op_24_d_intlk_p)
| start_10s_60s
| end_shift_cntrl
| end_acc_to_dist_ri
| tlu_on;
always @(posedge dp)
if (rst) begin
single_intlk <= 0;
end else if (man_prog_reset | all_restarts) begin
single_intlk <= 0;
end else if (single_intlk_set_p) begin
single_intlk <= 1;
end;
 
endmodule
ctl_commutator.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: operator_ctl.v =================================================================== --- operator_ctl.v (revision 26) +++ operator_ctl.v (revision 27) @@ -50,6 +50,7 @@ output reg pgm_start, pgm_stop, err_reset, err_sense_reset, output run_control, half_or_pgm_stop, ri_storage, ro_storage, storage_control, err_restart_sw, ovflw_stop_sw, ovflw_sense_sw, + pgm_stop_sw, output reg man_pgm_reset, man_acc_reset, hard_reset, output set_8000, reset_8000, @@ -83,6 +84,7 @@ assign err_restart_sw = err_sw_sense; assign ovflw_stop_sw = ovflw_sw_stop; assign ovflw_sense_sw = ovflw_sw_sense; + assign pgm_stop_sw = pgm_sw_stop; //----------------------------------------------------------------------------- // Calculate the RAM address of the general storage word at address gs_addr_. @@ -160,7 +162,7 @@ `define state_dump_gs_3 6'd60 `define state_dump_gs_4 6'd61 - always @(posedge clk) + always @(posedge dp, posedge rst) if (rst) begin console_to_addr <= 0; pgm_start <= 0; @@ -210,7 +212,7 @@ write_gs <= 0; acc_ri_console <= 0; console_out <= `biq_blank; - end else if (dp) begin + end else begin case (state) `state_idle: begin case (command)
/error_stop.v
37,10 → 37,10
err_stop_sig, restart_reset_busy,
output err_sense_light,
output reg err_stop_ed0u, err_sense_restart, restart_reset
output reg err_stop, err_stop_ed0u, err_sense_restart, restart_reset
);
reg err_stop, err_sense;
reg err_sense;
//-----------------------------------------------------------------------------
// The err_sense flip-flop does nothing but control a light.
/tlu.v
48,11 → 48,12
input sig_digit_on, hc_add_5, mult_on, acc_true_add_gate,
output tlu_on, early_dist_zero_entry, early_dist_zero_control,
output reg prog_ped_regen_latch, prog_to_acc_add, prog_add,
output reg prog_to_acc_add, prog_add,
output prog_add_d0,
output prog_ped_regen,
output [0:9] special_digit,
output tlu_band_change, dist_blank_gate
output tlu_band_change, dist_blank_gate, sel_stor_add_gate,
ontime_dist_add_gate, upper_lower_check
);
 
//-----------------------------------------------------------------------------
158,12 → 159,13
// When off, interrupts program register regeneration by blocking the path
// between program on time latch outputs and pedistal lines.
//-----------------------------------------------------------------------------
reg prog_ped_regen_latch;
assign prog_ped_regen = prog_ped_regen_latch; // & ~ap;
always @(posedge bp)
if (rst) begin
prog_ped_regen_latch <= 0;
end else if (~prog_add_on_p) begin
end else if (prog_add_on_p) begin
prog_ped_regen_latch <= 0;
end else if (dx) begin
prog_ped_regen_latch <= 1;
239,14 → 241,14
| (d5_tlu_carry_w0 & s1)
| prog_to_acc_add
| (acc_minus_sign & compl_adj)
| (quot_digit_on & edxl)
| (edxl & dist_compl_add)
| (~add_1 & any_left_shift_on & ~edxl);
| (quot_digit_on & dxl)
| (dxl & dist_compl_add)
| (~add_1 & any_left_shift_on & ~dxl);
wire add_1 = (tlu_carry_d4 & w2)
| (d5_tlu_carry_no_w0 & s1)
| (d5_tlu_carry_w0 & s2)
| (edxl & (right_shift_on | left_shift_on | mult_div_left_shift))
| (dist_compl_add & quot_digit_on & ed0l)
| (dxl & (right_shift_on | left_shift_on | mult_div_left_shift))
| (dist_compl_add & quot_digit_on & d0l)
| sig_digit_on;
wire add_2 = (tlu_carry_d4 & w3)
| (d5_tlu_carry_no_w0 & s2)
258,7 → 260,7
| (d5_tlu_carry_no_w0 & s4);
wire add_5 = (tlu_band_change & d5)
| (tlu_carry_d4 & w6)
| (edxl & hc_add_5);
| (dxl & hc_add_5);
wire add_6 = (tlu_carry_d4 & w7);
wire add_7 = (tlu_carry_d4 & w8);
wire add_8 = (tlu_carry_d4 & w9);
309,5 → 311,8
// gate from cathode follower 1036 for D1 through D10 of each word of the band
// except words 48 and 49.
//-----------------------------------------------------------------------------
assign sel_stor_add_gate = 1'b0;
assign ontime_dist_add_gate = 1'b0;
assign upper_lower_check = 1'b0;
endmodule
/addr_reg.v
43,7 → 43,7
input double_write,
input no_write,
input bs_to_gs,
input ri_gs,
input rigs,
input [0:6] ps_reg_in, console_in,
input ri_addr_reg,
input console_to_addr_reg,
121,7 → 121,7
assign addr_8xx3_p = addr_8xxx_p & addr_u[`biq_q3];
// Memory access error
assign mem_error_p = double_write | ((bs_to_gs | ri_gs) & ~dx & no_write);
assign mem_error_p = double_write | ((bs_to_gs | rigs) & ~dx & no_write);
always @(posedge ap)
if (rst) begin
/toplev.v
143,6 → 143,17
wire ca_acc_zero, ca_acc_no_zero, ca_check_latch;
 
//-----------------------------------------------------------------------------
// Control commutator
//-----------------------------------------------------------------------------
wire cc_restart_a, cc_restart_b, cc_i_alt, cc_d_alt, cc_man_stop_start,
cc_run_latch, cc_enable_ri, cc_man_ri_storage, cc_man_ro_storage,
cc_man_start_ri_dist_latch, cc_i_control_pulse, cc_i_control,
cc_d_control, cc_d_control_no_8001, cc_start_ri, cc_rips_ri_dist_intlk_a,
cc_rips_ri_dist_intlk_b, cc_op_intlk, cc_single_intlk, cc_rips,
cc_ri_dist, cc_acc_to_dist_ri_latch, cc_start_acc_to_dist_ri,
cc_end_acc_to_dist_ri, cc_rigs, cc_end_rigs;
//-----------------------------------------------------------------------------
// Register validity checking
//-----------------------------------------------------------------------------
wire ck_error_stop, ck_acc_check_light, ck_prog_check_light,
167,7 → 178,7
//-----------------------------------------------------------------------------
// Error stop
//-----------------------------------------------------------------------------
wire es_err_sense_light, es_err_stop_ed0u, es_err_sense_restart,
wire es_err_stop, es_err_sense_light, es_err_stop_ed0u, es_err_sense_restart,
es_restart_reset;
//-----------------------------------------------------------------------------
192,7 → 203,7
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
oc_storage_control, oc_err_restart_sw, oc_ovflw_stop_sw,
oc_ovflw_sense_sw;
oc_ovflw_sense_sw, oc_pgm_stop_sw;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
oc_hard_reset;
wire oc_restart_reset_busy;
210,6 → 221,15
wire [0:6] ss_selected_out;
//-----------------------------------------------------------------------------
// Table look-up
//-----------------------------------------------------------------------------
wire tl_tlu_on, tl_early_dist_zero_entry, tl_early_dist_zero_control,
tl_prog_to_acc_add, tl_prog_add, tl_prog_add_d0, tl_prog_ped_regen,
tl_tlu_band_change, tl_dist_blank_gate, tl_sel_stor_add_gate,
tl_ontime_dist_add_gate, tl_upper_lower_check;
wire [0:9] tl_special_digit;
//-----------------------------------------------------------------------------
// Translators
//-----------------------------------------------------------------------------
wire tr_gs_write;
232,7 → 252,7
.left_shift_gate(1'b0), //
.prog_step_add_gate(1'b0), //
.shift_num_gate(1'b0), //
.select_stor_add_gate(1'b0), //
.select_stor_add_gate(tl_sel_stor_add_gate),
.adder_entry_a(aa_entry_a)
);
239,11 → 259,11
add_in_b ab (
.dist_early_out(ds_early_out),
.dist_ontime_out(ds_ontime_out),
.special_int_entry(10'd0), //
.ontime_dist_add_gate_tlu(1'b0), //
.special_int_entry(tl_special_digit),
.ontime_dist_add_gate_tlu(tl_ontime_dist_add_gate),
.dist_compl_add_gate(1'b0), //
.upper_lower_check(1'b0), //
.dist_blank_gate(1'b0), //
.upper_lower_check(tl_upper_lower_check),
.dist_blank_gate(tl_dist_blank_gate),
.early_dist_zero_entry(1'b0), //
.dist_true_add_gate(1'b0), //
.adder_entry_b(ab_entry_b)
270,7 → 290,7
.acc_ri_console(oc_acc_ri_console),
.zero_shift_count(1'b0), //
.man_acc_reset(oc_man_acc_reset),
.reset_op(1'b0), //
.reset_op(dc_reset_sig),
.early_idx(early_idx),
.ontime_idx(ontime_idx),
.early_out(ac_early_out),
348,14 → 368,14
.s3(s3),
.s4(s4),
.error_reset(oc_err_reset),
.restart_a(1'b0), //
.restart_a(cc_restart_a),
.set_8000(oc_set_8000),
.reset_8000(oc_reset_8000),
.tlu_band_change(1'b0), //
.tlu_band_change(tl_tlu_band_change),
.double_write(gs_double_write),
.no_write(gs_no_write),
.bs_to_gs(1'b0), //
.ri_gs(1'b0), //
.rigs(cc_rigs),
.ps_reg_in(ps_ontime_out),
.console_in(oc_addr_out),
.ri_addr_reg(op_ri_addr_reg),
382,7 → 402,7
.d2(d2),
.d1_dx(d1_dx),
.acc_ped_out(ac_ped_out),
.sel_store_add_gate(1'b0), //
.sel_store_add_gate(tl_sel_stor_add_gate),
.err_reset(oc_err_reset),
.carry_test_latch(ad_carry_test),
.no_carry_test_latch(ad_no_carry_test),
391,6 → 411,80
.check_latch(ca_check_latch)
);
ctl_commutator cc (
.rst(oc_hard_reset),
.ap(ap),
.bp(bp),
.cp(cp),
.dp(dp),
.dx(dx),
.d1(d1),
.d3(d3),
.d7(d7),
.d9(d9),
.d10(d10),
.dxu(dxu),
.dxl(dxl),
.wu(wu),
.wl(wl),
.invalid_addr(ar_invalid_addr),
.man_prog_reset(oc_man_pgm_reset),
.run_control_sw(oc_run_control),
.program_start_sw(oc_pgm_start),
.manual_ri_storage_sw(oc_ri_storage),
.manual_ro_storage_sw(oc_ro_storage),
.manual_error_reset_sw(oc_err_reset),
.half_or_pgm_stop(oc_half_or_pgm_stop),
.prog_restart(ps_restart_sig),
.error_stop(es_err_stop),
.error_sense_restart(es_err_sense_restart),
.arith_restart(1'b0), //
.stop_code(dc_stop_code),
.code_69(dc_code_69),
.start_10s_60s(dc_turn_on_single_intlk),
.end_shift_cntrl(1'b0), //
.tlu_on(tl_tlu_on),
.end_of_operation(1'b0), //
.turn_on_op_intlk(dc_turn_on_op_intlk),
.decode_restarts(dc_all_restarts),
.use_d_for_i(dc_use_d_for_i),
.dist_back_signal(ds_back_sig),
.error_stop_ed0u(es_err_stop_ed0u),
.divide_overflow_stop(1'b0), //
.exceed_address_or_stor_select_light(1'b0), //
.opreg_t(op_opreg_t),
.opreg_u(op_opreg_u),
.addr_no_800x(ar_addr_no_800x),
.addr_8001(ar_addr_8001),
.dynamic_addr_hit(ar_dynamic_addr_hit),
.restart_a(cc_restart_a),
.restart_b(cc_restart_b),
.i_alt(cc_i_alt),
.d_alt(cc_d_alt),
.manual_stop_start(cc_man_stop_start),
.run_latch(cc_run_latch),
.enable_ri(cc_enable_ri),
.manual_ri_storage(cc_man_ri_storage),
.manual_ro_storage(cc_man_ro_storage),
.manual_start_ri_dist_latch(cc_man_start_ri_dist_latch),
.i_control_pulse(cc_i_control_pulse),
.i_control(cc_i_control),
.d_control(cc_d_control),
.d_control_no_8001(cc_d_control_no_8001),
.start_ri(cc_start_ri),
.rips_ri_dist_intlk_a(cc_rips_ri_dist_intlk_a),
.rips_ri_dist_intlk_b(cc_rips_ri_dist_intlk_b),
.op_intlk(cc_op_intlk),
.single_intlk(cc_single_intlk),
.rips(cc_rips),
.ri_dist(cc_ri_dist),
.acc_to_dist_ri_latch(cc_acc_to_dist_ri_latch),
.start_acc_to_dist_ri(cc_start_acc_to_dist_ri),
.end_acc_to_dist_ri(cc_end_acc_to_dist_ri),
.rigs(cc_rigs),
.end_rigs(cc_end_rigs)
);
checking ck (
.rst(oc_hard_reset),
.bp(bp),
405,7 → 499,8
.prog_check_light(ck_prog_check_light),
.dist_check_light(ck_dist_check_light)
);
decode_ctl dc (
decode_ctl dc (
.rst(oc_hard_reset),
.ap(ap),
.bp(bp),
431,16 → 526,16
.opreg_u(op_opreg_u),
.addr_u(ar_addr_u),
.ontime_dist(ds_ontime_out),
.man_ro_storage(1'b0), //
.man_ro_storage(cc_man_ro_storage),
.dist_back_sig(ds_back_sig),
.d_control(1'b0), //
.d_control(cc_d_control),
.ena_arith_codes(1'b0), //
.pgm_stop_sw(pgm_stop_sw), // ***
.pgm_stop_sw(oc_pgm_stop_sw),
.acc_zero_test(zc_acc_zero_test),
.acc_no_zero_test(zc_acc_no_zero_test),
.acc_plus_test(1'b0), //
.acc_minus_test(1'b0), //
.single_intlk(1'b0), //
.single_intlk(cc_single_intlk),
.arith_restart(1'b0), //
.overflow_sense_sig(ad_overflow_sense_sig),
.man_acc_reset(oc_man_acc_reset),
477,11 → 572,11
.d0(d0),
.d10(d10),
.selected_storage(ss_selected_out),
.ri_dist(1'd0), //
.ri_dist(cc_ri_dist),
.acc_ontime(ac_ontime_out),
.start_acc_dist_ri(1'd0), //
.end_acc_dist_ri(1'd0),
.acc_dist_ri(1'd0), //
.start_acc_dist_ri(cc_start_acc_to_dist_ri),
.end_acc_dist_ri(cc_end_acc_to_dist_ri),
.acc_dist_ri(cc_acc_to_dist_ri_latch),
.man_acc_reset(oc_man_acc_reset),
.early_idx(early_idx),
.ontime_idx(ontime_idx),
503,6 → 598,7
.clock_err_sig(1'b0), //
.err_stop_sig(ck_error_stop),
.restart_reset_busy(oc_restart_reset_busy),
.err_stop(es_err_stop),
.err_sense_light(es_err_sense_light),
.err_stop_ed0u(es_err_stop_ed0u),
.err_sense_restart(es_err_sense_restart),
576,6 → 672,7
.err_restart_sw(oc_err_restart_sw),
.ovflw_stop_sw(oc_ovflw_stop_sw),
.ovflw_sense_sw(oc_ovflw_sense_sw),
.pgm_stop_sw(oc_pgm_stop_sw),
.man_pgm_reset(oc_man_pgm_reset),
.man_acc_reset(oc_man_acc_reset),
.set_8000(oc_set_8000),
598,11 → 695,11
.d10(d10),
.d1_d5(d1_d5),
.d5_dx(d5_dx),
.restart_a(1'b0), //
.restart_b(1'b0), //
.d_alt(1'b0), //
.i_alt(1'b0), //
.tlu_band_change(1'b0), //
.restart_a(cc_restart_a),
.restart_b(cc_restart_b),
.d_alt(cc_d_alt),
.i_alt(cc_i_alt),
.tlu_band_change(tl_tlu_band_change),
.man_prog_reset(oc_man_pgm_reset),
.prog_step_ped(ps_ped_out),
.opreg_t(op_opreg_t),
620,11 → 717,11
.early_idx(early_idx),
.ontime_idx(ontime_idx),
.man_prog_reset(oc_man_pgm_reset),
.rips(1'b0), //
.rips(cc_rips),
.adder_out(ad_adder_out),
.sel_store_out(ss_selected_out),
.prog_ped_regen(1'b1), //
.prog_add(1'b0), //
.prog_ped_regen(tl_prog_ped_regen),
.prog_add(tl_prog_add),
.early_out(ps_early_out),
.ontime_out(ps_ontime_out),
.ped_out(ps_ped_out),
638,7 → 735,7
.addr_8000(ar_addr_8000),
.addr_8001(ar_addr_8001),
.addr_8002_8003(ar_addr_8002_8003),
.addr_hot_8000(1'b0), //
.addr_hot_8000(1'b0), // *** see cc
.acc_ontime(ac_ontime_out),
.dist_ontime(ds_ontime_out),
.gs_out(tr_gs_out),
648,11 → 745,77
.selected_out(ss_selected_out)
);
 
tlu tl (
.rst(oc_hard_reset),
.ap(ap),
.bp(bp),
.dx(dx),
.d0(d0),
.d4(d4),
.d5(d5),
.d10(d10),
.dxl(dxl),
.d0l(d0l),
.d10u(d10u),
.w0(w0),
.w1(w1),
.w2(w2),
.w3(w3),
.w4(w4),
.w5(w5),
.w6(w6),
.w7(w7),
.w8(w8),
.w9(w9),
.wl(wl),
.wu(wu),
.s0(s0),
.s1(s1),
.s2(s2),
.s3(s3),
.s4(s4),
.tlu_sig(dc_tlu_sig),
.upper_sig(dc_upper_sig),
.lower_sig(dc_lower_sig),
.divide_on(1'b0), //
.mult_nozero_edxl(1'b0), //
.carry_test_latch(ad_carry_test),
.tlu_or_acc_zero_check(ca_check_latch),
.man_acc_reset(oc_man_acc_reset),
.reset_sig(dc_reset_sig),
.no_reset_sig(dc_no_reset_sig),
.acc_minus_sign(1'b0), //
.compl_adj(1'b0), //
.quot_digit_on(1'b0), //
.dist_compl_add(1'b0), //
.any_left_shift_on(1'b0), //
.right_shift_on(1'b0), //
.left_shift_on(1'b0), //
.mult_div_left_shift(1'b0), //
.sig_digit_on(1'b0), //
.hc_add_5(1'b0), //
.mult_on(1'b0), //
.acc_true_add_gate(1'b0), //
.tlu_on(tl_tlu_on),
.early_dist_zero_entry(tl_early_dist_zero_entry),
.early_dist_zero_control(tl_early_dist_zero_control),
.prog_to_acc_add(tl_prog_to_acc_add),
.prog_add(tl_prog_add),
.prog_add_d0(tl_prog_add_d0),
.prog_ped_regen(tl_prog_ped_regen),
.special_digit(tl_special_digit),
.tlu_band_change(tl_tlu_band_change),
.dist_blank_gate(tl_dist_blank_gate),
.sel_stor_add_gate(tl_sel_stor_add_gate),
.ontime_dist_add_gate(tl_ontime_dist_add_gate),
.upper_lower_check(tl_upper_lower_check)
);
 
translators tr (
.dist_early_out(`biq_blank),
.bs_out(`biq_blank),
.console_out(oc_console_out),
.ri_gs(1'b0), //
.ri_gs(cc_rigs),
.ri_bs(1'b0), //
.ri_console(oc_write_gs),
.n800x(ar_addr_no_800x),

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