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    /i650/trunk/rtl
    from Rev 8 to Rev 9
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Rev 8 → Rev 9

/translators.v
0,0 → 1,56
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Drum code translators.
//
// Additional Comments:
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module translators (
input [0:6] dist_early_out,
input [0:6] bs_out,
input ri_gs,
input ri_bs,
input n800x,
input [0:4] gs_out,
output gs_write,
output [0:4] gs_in,
output reg[0:6] select_out
);
 
reg [0:6] sel_in7;
wire [0:6] sel_out7;
xlate7to5 x75 (sel_in7, gs_in);
xlate5to7 x57 (gs_out, sel_out7);
assign gs_write = ri_gs | ri_bs;
always @(*) begin
sel_in7 = (ri_gs)? dist_early_out : ((ri_bs)? bs_out : `biq_blank);
select_out = (n800x)? sel_out7 : `biq_blank;
end;
 
endmodule
translators.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xlate5to7.v =================================================================== --- xlate5to7.v (nonexistent) +++ xlate5to7.v (revision 9) @@ -0,0 +1,53 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// IBM 650 Reconstruction in Verilog (i650) +// +// This file is part of the IBM 650 Reconstruction in Verilog (i650) project +// http:////www.opencores.org/project,i650 +// +// Description: Translate 2-of-5 drum code to bi-quinary. +// +// Additional Comments: +// +// Copyright (c) 2015 Robert Abeles +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// +// This source is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +// PURPOSE. See the GNU Lesser General Public License for more +// details. +// +// You should have received a copy of the GNU Lesser General +// Public License along with this source; if not, download it +// from http://www.opencores.org/lgpl.shtml +////////////////////////////////////////////////////////////////////////////////// +`include "defines.v" + +module xlate5to7( + input [0:4] in_5, + output reg[0:6] out_7 + ); + + always @(*) begin + case (in_5) + `drum2of5_0 : out_7 = `biq_0; + `drum2of5_1 : out_7 = `biq_1; + `drum2of5_2 : out_7 = `biq_2; + `drum2of5_3 : out_7 = `biq_3; + `drum2of5_4 : out_7 = `biq_4; + `drum2of5_5 : out_7 = `biq_5; + `drum2of5_6 : out_7 = `biq_6; + `drum2of5_7 : out_7 = `biq_7; + `drum2of5_8 : out_7 = `biq_8; + `drum2of5_9 : out_7 = `biq_9; + default : out_7 = `biq_blank; // invalid codes become all zeroes + endcase; + end; + +endmodule
xlate5to7.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xlate7to5.v =================================================================== --- xlate7to5.v (nonexistent) +++ xlate7to5.v (revision 9) @@ -0,0 +1,52 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// IBM 650 Reconstruction in Verilog (i650) +// +// This file is part of the IBM 650 Reconstruction in Verilog (i650) project +// http:////www.opencores.org/project,i650 +// +// Description: Translate bi-quinary to 2-of-5 drum code. +// +// Additional Comments: +// +// Copyright (c) 2015 Robert Abeles +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// +// This source is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +// PURPOSE. See the GNU Lesser General Public License for more +// details. +// +// You should have received a copy of the GNU Lesser General +// Public License along with this source; if not, download it +// from http://www.opencores.org/lgpl.shtml +////////////////////////////////////////////////////////////////////////////////// +`include "defines.v" + +module xlate7to5( + input [0:6] in_7, + output reg[0:4] out_5 + ); + + always @(*) begin + case (in_7) + `biq_0 : out_5 = `drum2of5_0; + `biq_1 : out_5 = `drum2of5_1; + `biq_2 : out_5 = `drum2of5_2; + `biq_3 : out_5 = `drum2of5_3; + `biq_4 : out_5 = `drum2of5_4; + `biq_5 : out_5 = `drum2of5_5; + `biq_6 : out_5 = `drum2of5_6; + `biq_7 : out_5 = `drum2of5_7; + `biq_8 : out_5 = `drum2of5_8; + `biq_9 : out_5 = `drum2of5_9; + default : out_5 = `drum2of5_blank; // invalid codes become zeroes + endcase; + end; +endmodule
xlate7to5.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: operator_ctl.v =================================================================== --- operator_ctl.v (revision 8) +++ operator_ctl.v (revision 9) @@ -43,6 +43,7 @@ output reg[0:6] data_out, addr_out, output reg console_to_addr, output reg[0:14] gs_ram_addr, + output reg read_gs, write_gs, output reg pgm_start, pgm_stop, err_reset, err_sense_reset, output run_control, half_or_pgm_stop, ri_storage, ro_storage, storage_control, @@ -75,9 +76,9 @@ reg [0:5] state; reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u; - wire [0:14] gs_band_addr, gs_word_offset; - ram_band_addr rba(gs_addr_th[`biq_q1], gs_addr_h, gs_addr_t[`biq_b5], - gs_band_addr); + wire [0:14] gs_band_addr; + wire [0:9] gs_word_offset; + ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr); ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset); wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset; @@ -110,6 +111,7 @@ `define state_read_gs_2 6'd32 `define state_read_gs_3 6'd33 `define state_read_gs_4 6'd34 + `define state_read_gs_5 6'd35 //----------------------------------------------------------------------------- // Operator console state machine @@ -156,7 +158,8 @@ do_acc_reset <= 0; gs_ram_addr <= 15'd0; - + read_gs <= 0; + write_gs <= 0; end else begin case (state) `state_idle: begin @@ -394,17 +397,44 @@ state <= `state_read_gs_1; end end - `ifdef 0 - `cmd_write_gs: - `cmd_read_acc: - `cmd_read_dist: - `cmd_read_prog: - `cmd_clear_gs: - `cmd_load_gs: - `cmd_dump_gs: - `cmd_power_on_reset: - `cmd_reset_console: - `endif + + + `cmd_write_gs: begin + end + + `cmd_read_acc: begin + end + + `cmd_read_dist: begin + end + + `cmd_read_prog: begin + end + + // 0 : Ignore if not in manual + // Clear gs_ram_addr + // 1 : Synchronize with d10 + // Turn on console_write_gs + // 2 : Put a digit: + // dx: blank + // d0: minus + // d1-d10: zero + // gs_ram_addr++ + `cmd_clear_gs: begin + + end + + `cmd_load_gs: begin + end + + `cmd_dump_gs: begin + end + + `cmd_power_on_reset: begin + end + + `cmd_reset_console: begin + end endcase; end @@ -590,6 +620,11 @@ gs_ram_addr <= gs_word_addr; state <= `state_read_gs_4; end + + `state_read_gs_4: begin + + state <= `state_read_gs_5; + end endcase; end
/ram_band_addr.v
31,16 → 31,15
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module ram_band_addr (
input addr_th_q1,
input [0:6] addr_h,
input addr_t_b5,
input [0:6] addr_th, addr_h, addr_t,
output reg [0:14] origin
);
always @(*) begin
case({addr_th_q1, addr_h, addr_t_b5})
case ({addr_th[`biq_q1], addr_h, addr_t[`biq_b5]})
9'b0_01_00001_0: origin = 15'd0;
9'b0_01_00001_1: origin = 15'd600;
9'b0_01_00010_0: origin = 15'd1200;
/ram_word_offset.v
32,65 → 32,65
 
module ram_word_offset (
input [0:6] addr_t, addr_u,
output reg [0:14] offset
output reg [0:9] offset
);
always @(*) begin
case({addr_t[2:6], addr_u})
12'b00001_01_00001: offset = 15'd0;
12'b00001_01_00010: offset = 15'd12;
12'b00001_01_00100: offset = 15'd24;
12'b00001_01_01000: offset = 15'd36;
12'b00001_01_10000: offset = 15'd48;
12'b00001_10_00001: offset = 15'd60;
12'b00001_10_00010: offset = 15'd72;
12'b00001_10_00100: offset = 15'd84;
12'b00001_10_01000: offset = 15'd96;
12'b00001_10_10000: offset = 15'd108;
12'b00001_01_00001: offset = 10'd0;
12'b00001_01_00010: offset = 10'd12;
12'b00001_01_00100: offset = 10'd24;
12'b00001_01_01000: offset = 10'd36;
12'b00001_01_10000: offset = 10'd48;
12'b00001_10_00001: offset = 10'd60;
12'b00001_10_00010: offset = 10'd72;
12'b00001_10_00100: offset = 10'd84;
12'b00001_10_01000: offset = 10'd96;
12'b00001_10_10000: offset = 10'd108;
 
12'b00010_01_00001: offset = 15'd120;
12'b00010_01_00010: offset = 15'd132;
12'b00010_01_00100: offset = 15'd144;
12'b00010_01_01000: offset = 15'd156;
12'b00010_01_10000: offset = 15'd168;
12'b00010_10_00001: offset = 15'd180;
12'b00010_10_00010: offset = 15'd192;
12'b00010_10_00100: offset = 15'd204;
12'b00010_10_01000: offset = 15'd216;
12'b00010_10_10000: offset = 15'd228;
12'b00010_01_00001: offset = 10'd120;
12'b00010_01_00010: offset = 10'd132;
12'b00010_01_00100: offset = 10'd144;
12'b00010_01_01000: offset = 10'd156;
12'b00010_01_10000: offset = 10'd168;
12'b00010_10_00001: offset = 10'd180;
12'b00010_10_00010: offset = 10'd192;
12'b00010_10_00100: offset = 10'd204;
12'b00010_10_01000: offset = 10'd216;
12'b00010_10_10000: offset = 10'd228;
 
12'b00100_01_00001: offset = 15'd240;
12'b00100_01_00010: offset = 15'd252;
12'b00100_01_00100: offset = 15'd264;
12'b00100_01_01000: offset = 15'd276;
12'b00100_01_10000: offset = 15'd288;
12'b00100_10_00001: offset = 15'd300;
12'b00100_10_00010: offset = 15'd312;
12'b00100_10_00100: offset = 15'd324;
12'b00100_10_01000: offset = 15'd336;
12'b00100_10_10000: offset = 15'd348;
12'b00100_01_00001: offset = 10'd240;
12'b00100_01_00010: offset = 10'd252;
12'b00100_01_00100: offset = 10'd264;
12'b00100_01_01000: offset = 10'd276;
12'b00100_01_10000: offset = 10'd288;
12'b00100_10_00001: offset = 10'd300;
12'b00100_10_00010: offset = 10'd312;
12'b00100_10_00100: offset = 10'd324;
12'b00100_10_01000: offset = 10'd336;
12'b00100_10_10000: offset = 10'd348;
 
12'b01000_01_00001: offset = 15'd360;
12'b01000_01_00010: offset = 15'd372;
12'b01000_01_00100: offset = 15'd384;
12'b01000_01_01000: offset = 15'd396;
12'b01000_01_10000: offset = 15'd408;
12'b01000_10_00001: offset = 15'd420;
12'b01000_10_00010: offset = 15'd432;
12'b01000_10_00100: offset = 15'd444;
12'b01000_10_01000: offset = 15'd456;
12'b01000_10_10000: offset = 15'd468;
12'b01000_01_00001: offset = 10'd360;
12'b01000_01_00010: offset = 10'd372;
12'b01000_01_00100: offset = 10'd384;
12'b01000_01_01000: offset = 10'd396;
12'b01000_01_10000: offset = 10'd408;
12'b01000_10_00001: offset = 10'd420;
12'b01000_10_00010: offset = 10'd432;
12'b01000_10_00100: offset = 10'd444;
12'b01000_10_01000: offset = 10'd456;
12'b01000_10_10000: offset = 10'd468;
 
12'b10000_01_00001: offset = 15'd480;
12'b10000_01_00010: offset = 15'd492;
12'b10000_01_00100: offset = 15'd504;
12'b10000_01_01000: offset = 15'd516;
12'b10000_01_10000: offset = 15'd528;
12'b10000_10_00001: offset = 15'd540;
12'b10000_10_00010: offset = 15'd552;
12'b10000_10_00100: offset = 15'd564;
12'b10000_10_01000: offset = 15'd576;
12'b10000_10_10000: offset = 15'd588;
12'b10000_01_00001: offset = 10'd480;
12'b10000_01_00010: offset = 10'd492;
12'b10000_01_00100: offset = 10'd504;
12'b10000_01_01000: offset = 10'd516;
12'b10000_01_10000: offset = 10'd528;
12'b10000_10_00001: offset = 10'd540;
12'b10000_10_00010: offset = 10'd552;
12'b10000_10_00100: offset = 10'd564;
12'b10000_10_01000: offset = 10'd576;
12'b10000_10_10000: offset = 10'd588;
 
default: offset = 15'd0;
endcase;
/gen_store.v
0,0 → 1,75
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: General storage.
//
// Additional Comments: Drum storage is implemented as an array of 24000 5-bit
// digits. An array address is formed by decoding the static portion of the
// bi-quinary address into an origin (a multiple of 600), then adding the
// dynamic portion of the address (range 0..599).
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module gen_store (
input rst,
input ap, dp,
input write_gate,
input [0:6] addr_th, addr_h, addr_t,
input [0:9] dynamic_addr,
input [0:4] gs_in,
input [0:14] console_ram_addr,
input console_read_gs, console_write_gs,
output reg[0:4] gs_out,
output double_write, no_write
);
 
reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
wire [0:14] band_addr, gs_addr, gs_addr_early;
ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
wire console_access = console_read_gs | console_write_gs;
assign gs_addr = console_access? console_ram_addr : (band_addr + dynamic_addr);
assign gs_addr_early = (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
assign double_write = 0;
assign no_write = 0;
always @(posedge ap) begin
if (rst) begin
gs_out <= `biq_blank;
end else begin
gs_out <= gs_mem[gs_addr];
end
end;
always @(posedge dp) begin
if (write_gate)
gs_mem[gs_addr_early] <= gs_in;
end;
endmodule
gen_store.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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