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  • This comparison shows the changes necessary to convert path 
    /i650/trunk
    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/rtl/translators.v
30,10 → 30,8
`include "defines.v"
 
module translators (
input [0:6] dist_early_out,
input [0:6] bs_out,
input ri_gs,
input ri_bs,
input [0:6] dist_early_out, bs_out, console_out,
input ri_gs, ri_bs, ri_console,
input n800x,
input [0:4] gs_out,
output gs_write,
46,10 → 44,13
xlate7to5 x75 (sel_in7, gs_in);
xlate5to7 x57 (gs_out, sel_out7);
assign gs_write = ri_gs | ri_bs;
assign gs_write = ri_gs | ri_bs | ri_console;
always @(*) begin
sel_in7 = (ri_gs)? dist_early_out : ((ri_bs)? bs_out : `biq_blank);
sel_in7 = ri_console? console_out
: ri_gs? dist_early_out
: ri_bs? bs_out
: `biq_blank;
select_out = (n800x)? sel_out7 : `biq_blank;
end;
 
/rtl/defines.v
117,4 → 117,5
`define cmd_dump_gs 6'd35
// resets
`define cmd_power_on_reset 6'd36
`define cmd_reset_console 6'd37
`define cmd_reset_console 6'd37
`define cmd_hard_reset 6'd38
/rtl/operator_ctl.v
31,16 → 31,16
`include "defines.v"
 
module operator_ctl (
input rst,
input rst, clk,
input ap, dp,
input dx, d0, d1, d2, d3, d4, d5, d6, d10,
input wu, hp,
input [0:3] early_idx, ontime_idx,
input [0:6] cmd_digit_in, io_buffer_in,
input [0:6] cmd_digit_in, io_buffer_in, gs_in,
input [0:5] command,
output reg[0:6] data_out, addr_out,
output reg[0:6] data_out, addr_out, console_out,
output reg console_to_addr,
output reg[0:14] gs_ram_addr,
output reg read_gs, write_gs,
48,6 → 48,7
output run_control, half_or_pgm_stop, ri_storage, ro_storage,
storage_control,
output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
hard_reset,
output reg[0:6] cmd_digit_out,
output reg busy, digit_ready,
72,7 → 73,7
assign storage_control = run_control | disp_sw_ro;
reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
do_pgm_reset, do_acc_reset;
do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
reg [0:5] state;
reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
94,29 → 95,34
`define state_err_reset_2 6'd8
`define state_err_sense_reset_1 6'd9
`define state_err_sense_reset_2 6'd10
`define state_hard_reset_1 6'd11
 
`define state_storage_entry_sw_1 6'd11
`define state_storage_entry_sw_2 6'd12
`define state_addr_sel_sw_1 6'd13
`define state_addr_sel_sw_2 6'd14
`define state_storage_entry_sw_1 6'd12
`define state_storage_entry_sw_2 6'd13
`define state_addr_sel_sw_1 6'd14
`define state_addr_sel_sw_2 6'd15
`define state_xfer_key_1 6'd15
`define state_xfer_key_2 6'd16
`define state_pgm_start_key_1 6'd17
`define state_pgm_start_key_2 6'd18
`define state_pgm_stop_key_1 6'd19
`define state_pgm_stop_key_2 6'd20
`define state_xfer_key_1 6'd16
`define state_xfer_key_2 6'd17
`define state_pgm_start_key_1 6'd18
`define state_pgm_start_key_2 6'd19
`define state_pgm_stop_key_1 6'd20
`define state_pgm_stop_key_2 6'd21
`define state_read_gs_1 6'd31
`define state_read_gs_2 6'd32
`define state_read_gs_3 6'd33
`define state_read_gs_4 6'd34
`define state_read_gs_5 6'd35
`define state_read_gs_1 6'd30
`define state_read_gs_2 6'd31
`define state_read_gs_3 6'd32
`define state_read_gs_4 6'd33
`define state_read_gs_5 6'd34
`define state_clear_drum_1 6'd50
`define state_clear_drum_2 6'd51
`define state_clear_drum_3 6'd52
//-----------------------------------------------------------------------------
// Operator console state machine
//-----------------------------------------------------------------------------
always @(posedge rst, posedge dp) begin
always @(posedge clk) begin
if (rst) begin
console_to_addr <= 0;
pgm_start <= 0;
127,10 → 133,13
man_acc_reset <= 0;
set_8000 <= 0;
reset_8000 <= 0;
hard_reset <= 0;
// reset console switches
pgm_sw_stop <= 0;
pgm_sw_run <= 1;
half_cycle_sw_run <= 1;
half_cycle_sw_half <= 0;
ctl_sw_addr_stop <= 0;
ctl_sw_run <= 1;
ctl_sw_manual <= 0;
156,11 → 165,14
do_err_sense_reset <= 0;
do_pgm_reset <= 0;
do_acc_reset <= 0;
do_hard_reset <= 0;
do_clear_drum <= 0;
gs_ram_addr <= 15'd0;
read_gs <= 0;
write_gs <= 0;
end else begin
console_out <= `biq_blank;
end else if (dp) begin
case (state)
`state_idle: begin
case (command)
172,9 → 184,19
do_acc_reset <= 1;
do_err_reset <= 1;
do_err_sense_reset <= 1;
do_hard_reset <= 1;
do_clear_drum <= 1;
end else if (do_hard_reset) begin
do_hard_reset <= 0;
hard_reset <= 1;
state <= `state_hard_reset_1;
end else if (do_reset_console) begin
do_reset_console <= 0;
state <= `state_reset_console_1;
end else if (do_clear_drum) begin
do_clear_drum <= 0;
gs_ram_addr <= 15'd0;
state <= `state_clear_drum_1;
end else if (do_pgm_reset) begin
do_pgm_reset <= 0;
state <= `state_pgm_reset_1;
354,11 → 376,13
end
`cmd_pgm_reset_key: begin
busy <= 1;
do_pgm_reset <= 1;
do_err_reset <= 1;
end
 
`cmd_comp_reset_key: begin
busy <= 1;
do_pgm_reset <= 1;
do_acc_reset <= 1;
do_err_reset <= 1;
365,15 → 389,18
end
`cmd_acc_reset_key: begin
busy <= 1;
do_acc_reset <= 1;
do_err_reset <= 1;
end
`cmd_err_reset_key: begin
busy <= 1;
do_err_reset <= 1;
end
`cmd_err_sense_reset_key: begin
busy <= 1;
do_err_sense_reset <= 1;
end
421,7 → 448,10
// d1-d10: zero
// gs_ram_addr++
`cmd_clear_gs: begin
if (ctl_sw_manual) begin
busy <= 1;
do_clear_drum <= 1;
end
end
`cmd_load_gs: begin
436,6 → 466,11
`cmd_reset_console: begin
end
`cmd_hard_reset: begin
busy <= 1;
do_hard_reset <= 1;
end
endcase;
end
445,7 → 480,8
end
`state_reset_console_2: begin
storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
storage_entry_sw[ontime_idx] <= dx? `biq_blank
: d0? `biq_plus : `biq_0;
addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
if (d10) state <= `state_idle;
end
510,6 → 546,12
end
end
// Hard reset
`state_hard_reset_1: begin
hard_reset <= 0;
state <= `state_idle;
end
// Set storage entry switches
`state_storage_entry_sw_1: begin
if (d0) begin
622,16 → 664,44
end
`state_read_gs_4: begin
cmd_digit_out <= gs_in;
state <= `state_read_gs_5;
end
// 0 : Ignore if not in manual
// Clear gs_ram_addr
// 1 : Synchronize with d10
// Turn on console_write_gs
// 2 : Put a digit:
// dx: blank
// d0: minus
// d1-d10: zero
// gs_ram_addr++
`state_clear_drum_1: begin
if (d10) begin
state <= `state_clear_drum_2;
end
end
`state_clear_drum_2: begin
write_gs <= 1;
console_out <= dx? `biq_blank
: d0? `biq_minus
: `biq_0;
if (write_gs)
gs_ram_addr <= gs_ram_addr + 1;
if (gs_ram_addr == 15'd23999) begin
write_gs <= 0;
state <= `state_idle;
end
end
endcase;
end
end;
always @(posedge rst, posedge ap) begin
if (rst) begin
always @(posedge ap) begin
if (hard_reset) begin
data_out <= `biq_blank;
addr_out <= `biq_blank;
end else begin
640,8 → 710,8
end
end;
always @(posedge rst, posedge ap) begin
if (rst) begin
always @(posedge ap) begin
if (hard_reset) begin
punch_card <= 0;
read_card <= 0;
card_digit_ready <= 0;
/rtl/gen_store.v
52,9 → 52,10
//-----------------------------------------------------------------------------
wire [0:14] band_addr, gs_addr, gs_addr_early;
ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
wire console_access = console_read_gs | console_write_gs;
assign gs_addr = console_access? console_ram_addr : (band_addr + dynamic_addr);
assign gs_addr_early = (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
wire console_acc = console_read_gs | console_write_gs;
assign gs_addr = console_acc? console_ram_addr : (band_addr + dynamic_addr);
assign gs_addr_early = console_acc? console_ram_addr
: (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
assign double_write = 0;
assign no_write = 0;

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