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    /idea/trunk/fsm/key_regulator
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Rev 6 → Rev 9

/ctr_enkeyx.fsm
0,0 → 1,233
--Nama file : ctr_enkeyx.fsm
--Deskripsi : blok kontroller kunci enkripsi
--Author : Mas Adit
--Tanggal : 21 Agustus 2001
 
entity ctr_enkeyx is
port (
clk : in bit;
rst : in bit;
start : in bit;
count : in bit_vector(2 downto 0);
en_shft : out bit;
en_count : out bit;
sel1 : out bit;
sel2 : out bit;
c_count : out bit;
finish : out bit;
en_out : out bit;
vdd : in bit;
vss : in bit
);
end ctr_enkeyx;
 
architecture STATE_MACHINE of ctr_enkeyx is
 
type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10);
 
--pragma CLOCK clk
--pragma CURRENT_STATE CURRENT_STATE
--pragma NEXT_STATE NEXT_STATE
 
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
 
begin
process (CURRENT_STATE, rst, start, count)
begin
if rst then
NEXT_STATE <= S0;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '0';
else
case CURRENT_STATE is
when S0 =>
if start then
if (count = "000") then
NEXT_STATE <= S1;
en_shft <= '0';
en_count <= '1';
en_out <= '1';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
 
else
if (count = "001") then
NEXT_STATE <= S3;
en_shft <= '1';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
 
else
if (count = "111") then
NEXT_STATE <= S10;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '1';
 
else
NEXT_STATE <= S6;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '0';
 
end if;
end if;
end if;
 
else
NEXT_STATE <= S0;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '0';
 
end if;
 
when S1 =>
NEXT_STATE <= S2;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
 
when S2 =>
NEXT_STATE <= S2;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
 
when S3 =>
NEXT_STATE <= S4;
en_shft <= '0';
en_count <= '1';
en_out <= '1';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
 
when S4 =>
NEXT_STATE <= S5;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
 
when S5 =>
NEXT_STATE <= S5;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
 
when S6 =>
NEXT_STATE <= S7;
en_shft <= '1';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
 
when S7 =>
NEXT_STATE <= S8;
en_shft <= '0';
en_count <= '1';
en_out <= '1';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
 
when S8 =>
NEXT_STATE <= S9;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
 
when S9 =>
NEXT_STATE <= S9;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
 
when S10 =>
NEXT_STATE <= S10;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '1';
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '0') and not(clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/kontrol_utama_invaddx.fsm
0,0 → 1,148
--Nama file : kontrol_utama_invaddx.fsm
--Deskripsi : kontrol utama modul inv_add modulo (2^16 + 1)
--Author : Mas Adit
--Tanggal : 28 Agustus 2001
 
entity kontrol_utama_invaddx is
port (
clk : in bit;
rst : in bit;
start : in bit;
n_dtin : in bit_vector(4 downto 0);
n_dtout : in bit_vector(4 downto 0);
c_cdtin : out bit;
en_cdtin : out bit;
c_cdtout : out bit;
en_cdtout : out bit;
en_out : out bit;
en_in : out bit;
finish : out bit;
vdd : in bit;
vss : in bit
);
end kontrol_utama_invaddx;
 
architecture fsm of kontrol_utama_invaddx is
 
type STATE_TYPE is (S0, S1, S2, S3, S4);
--pragma CLOCK clk
--pragma CURRENT_STATE CURRENT_STATE
--pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
 
begin
 
process (CURRENT_STATE, rst, start, n_dtout, n_dtin)
begin
if (rst = '1') then
NEXT_STATE <= S0;
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
finish <= '0';
else
case CURRENT_STATE is
 
when S0 =>
if (start = '1') then
if not(n_dtout = "10010") then
if (n_dtin = "00000") then
NEXT_STATE <= S1;
en_cdtin <= '1';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
finish <= '0';
else
NEXT_STATE <= S2;
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '1';
en_out <= '0';
finish <= '0';
end if;
else
NEXT_STATE <= S4;
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
finish <= '1';
end if;
else
NEXT_STATE <= S0;
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
finish <= '0';
end if;
 
when S1 =>
NEXT_STATE <= S3;
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
finish <= '0';
 
when S2 =>
NEXT_STATE <= S3;
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
finish <= '0';
 
when S3 =>
NEXT_STATE <= S3;
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
finish <= '0';
 
when S4 =>
NEXT_STATE <= S4;
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
finish <= '1';
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '0') and not(clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end fsm;
 
 
 
 
 
/kontrol_utama_invmulx.fsm
0,0 → 1,588
--Nama file : kontrol_utama_invmulx.fsm
--Deskripsi : koontrol utama inv_mul (2^16 + 1)
--Author : Mas Adit
--Tanggal : 26 Agustus 2001
 
entity kontrol_utama_invmulx is
port (
start : in bit;
clk : in bit;
rst : in bit;
n_stage : in bit_vector( 1 downto 0);
n_iterasi : in bit_vector(3 downto 0);
n_dtin : in bit_vector(4 downto 0);
n_dtout : in bit_vector(4 downto 0);
en_cstage : out bit;
c_cstage : out bit;
en_cite : out bit;
c_cite : out bit;
en_cdtin : out bit;
c_cdtin : out bit;
en_cdtout : out bit;
c_cdtout : out bit;
en_in : out bit;
en_out : out bit;
en_pipe : out bit;
sel : out bit;
finish : out bit;
vdd : in bit;
vss : in bit
);
end kontrol_utama_invmulx;
 
architecture STATE_MACHINE of kontrol_utama_invmulx is
 
type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21);
--pragma CLOCK clk
--pragma CURRENT_STATE CURRENT_STATE
--pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
 
begin
 
process (CURRENT_STATE, rst, start, n_dtout, n_iterasi, n_stage)
begin
if (rst = '1') then
NEXT_STATE <= S0;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
else
case CURRENT_STATE is
 
when S0 =>
if (start = '1') then
if not(n_dtout = "10010") then
NEXT_STATE <= S1;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '1';
else
if (n_iterasi = "0000") then
if (n_stage = "00") then
NEXT_STATE <= S2;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S4;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
end if;
else
if (n_iterasi = "1111") then
NEXT_STATE <= S16;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S10;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
end if;
end if;
end if;
else
NEXT_STATE <= S0;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
end if;
 
when S1 =>
NEXT_STATE <= S1;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '1';
 
when S2 =>
NEXT_STATE <= S3;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '1';
finish <= '0';
 
when S3 =>
NEXT_STATE <= S4;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
 
when S4 =>
if (n_stage = "10") then
NEXT_STATE <= S5;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
else
NEXT_STATE <= S6;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
end if;
 
when S5 =>
NEXT_STATE <= S7;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
 
when S6 =>
NEXT_STATE <= S8;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
 
when S7 =>
NEXT_STATE <= S9;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S8 =>
NEXT_STATE <= S9;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S9 =>
NEXT_STATE <= S9;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S10 =>
if (n_stage = "10") then
NEXT_STATE <= S11;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S12;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
end if;
 
when S11 =>
NEXT_STATE <= S13;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
 
when S12 =>
NEXT_STATE <= S14;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
 
when S13 =>
NEXT_STATE <= S15;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S14 =>
NEXT_STATE <= S15;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S15 =>
NEXT_STATE <= S15;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S16 =>
if (n_stage = "10") then
NEXT_STATE <= S17;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S18;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
end if;
 
when S17 =>
NEXT_STATE <= S19;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
 
when S18 =>
NEXT_STATE <= S20;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
 
when S19 =>
NEXT_STATE <= S21;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S20 =>
NEXT_STATE <= S21;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
when S21 =>
NEXT_STATE <= S21;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '0') and not(clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/count2x.fsm
0,0 → 1,61
--Nama file : count2x.fsm
--Deskripsi : counter 2 bit
--Author : Mas Adit
--Tanggal : 31 Agustus 2001
 
entity count2x is
port (
clk : in bit;
rst : in bit;
q : out bit_vector(1 downto 0);
vdd : in bit;
vss : in bit
);
end count2x;
 
architecture STATE_MACHINE of count2x is
 
type STATE_TYPE IS (S0, S1, S2, S3);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
begin
process ( CURRENT_STATE, rst )
begin
if ( rst = '1' ) then
NEXT_STATE <= S0;
q <= "00";
else
case CURRENT_STATE IS
when S0 =>
q <= "00";
NEXT_STATE <= S1;
when S1 =>
q <= "01";
NEXT_STATE <= S2;
when S2 =>
q <= "10";
NEXT_STATE <= S3;
when S3 =>
q <= "11";
NEXT_STATE <= S0;
when OTHERS =>
assert ( '1' )
report "Illegal State";
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and not (clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
/count3x.fsm
0,0 → 1,73
--Nama file : count3x.fsm
--Deskripsi : counter 3 bit
--Author : Mas Adit
--Tanggal : 31 Agustus 2001
 
entity count3x is
port (
clk : in bit;
rst : in bit;
q : out bit_vector(2 downto 0);
vdd : in bit;
vss : in bit
);
end count3x;
 
architecture STATE_MACHINE of count3x is
 
type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
begin
process ( CURRENT_STATE, rst )
begin
if ( rst = '1' ) then
NEXT_STATE <= S0;
q <= "000";
else
case CURRENT_STATE IS
when S0 =>
q <= "000";
NEXT_STATE <= S1;
when S1 =>
q <= "001";
NEXT_STATE <= S2;
when S2 =>
q <= "010";
NEXT_STATE <= S3;
when S3 =>
q <= "011";
NEXT_STATE <= S4;
when S4 =>
q <= "100";
NEXT_STATE <= S5;
when S5 =>
q <= "101";
NEXT_STATE <= S6;
when S6 =>
q <= "110";
NEXT_STATE <= S7;
when S7 =>
q <= "111";
NEXT_STATE <= S0;
when OTHERS =>
assert ( '1' )
report "Illegal State";
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and not (clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
/count4x.fsm
0,0 → 1,97
--Nama file : count4x.fsm
--Deskripsi : counter 4 bit
--Author : Mas Adit
--Tanggal : 31 Agustus 2001
 
entity count4x is
port (
clk : in bit;
rst : in bit;
q : out bit_vector(3 downto 0);
vdd : in bit;
vss : in bit
);
end count4x;
 
architecture STATE_MACHINE of count4x is
 
type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
begin
process ( CURRENT_STATE, rst )
begin
if ( rst = '1' ) then
NEXT_STATE <= S0;
q <= "0000";
else
case CURRENT_STATE IS
when S0 =>
q <= "0000";
NEXT_STATE <= S1;
when S1 =>
q <= "0001";
NEXT_STATE <= S2;
when S2 =>
q <= "0010";
NEXT_STATE <= S3;
when S3 =>
q <= "0011";
NEXT_STATE <= S4;
when S4 =>
q <= "0100";
NEXT_STATE <= S5;
when S5 =>
q <= "0101";
NEXT_STATE <= S6;
when S6 =>
q <= "0110";
NEXT_STATE <= S7;
when S7 =>
q <= "0111";
NEXT_STATE <= S8;
when S8 =>
q <= "1000";
NEXT_STATE <= S9;
when S9 =>
q <= "1001";
NEXT_STATE <= S10;
when S10 =>
q <= "1010";
NEXT_STATE <= S11;
when S11 =>
q <= "1011";
NEXT_STATE <= S12;
when S12 =>
q <= "1100";
NEXT_STATE <= S13;
when S13 =>
q <= "1101";
NEXT_STATE <= S14;
when S14 =>
q <= "1110";
NEXT_STATE <= S15;
when S15 =>
q <= "1111";
NEXT_STATE <= S0;
when OTHERS =>
assert ( '1' )
report "Illegal State";
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and not (clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
/count5x.fsm
0,0 → 1,145
--Nama file : count5x.fsm
--Deskripsi : counter 5 bit
--Author : Mas Adit
--Tanggal : 31 Agustus 2001
 
entity count5x is
port (
clk : in bit;
rst : in bit;
q : out bit_vector(4 downto 0);
vdd : in bit;
vss : in bit
);
end count5x;
 
architecture STATE_MACHINE of count5x is
 
type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
begin
process ( CURRENT_STATE, rst )
begin
if ( rst = '1' ) then
NEXT_STATE <= S0;
q <= "00000";
else
case CURRENT_STATE IS
when S0 =>
q <= "00000";
NEXT_STATE <= S1;
when S1 =>
q <= "00001";
NEXT_STATE <= S2;
when S2 =>
q <= "00010";
NEXT_STATE <= S3;
when S3 =>
q <= "00011";
NEXT_STATE <= S4;
when S4 =>
q <= "00100";
NEXT_STATE <= S5;
when S5 =>
q <= "00101";
NEXT_STATE <= S6;
when S6 =>
q <= "00110";
NEXT_STATE <= S7;
when S7 =>
q <= "00111";
NEXT_STATE <= S8;
when S8 =>
q <= "01000";
NEXT_STATE <= S9;
when S9 =>
q <= "01001";
NEXT_STATE <= S10;
when S10 =>
q <= "01010";
NEXT_STATE <= S11;
when S11 =>
q <= "01011";
NEXT_STATE <= S12;
when S12 =>
q <= "01100";
NEXT_STATE <= S13;
when S13 =>
q <= "01101";
NEXT_STATE <= S14;
when S14 =>
q <= "01110";
NEXT_STATE <= S15;
when S15 =>
q <= "01111";
NEXT_STATE <= S16;
when S16 =>
q <= "10000";
NEXT_STATE <= S17;
when S17 =>
q <= "10001";
NEXT_STATE <= S18;
when S18 =>
q <= "10010";
NEXT_STATE <= S19;
when S19 =>
q <= "10011";
NEXT_STATE <= S20;
when S20 =>
q <= "10100";
NEXT_STATE <= S21;
when S21 =>
q <= "10101";
NEXT_STATE <= S22;
when S22 =>
q <= "10110";
NEXT_STATE <= S23;
when S23 =>
q <= "10111";
NEXT_STATE <= S24;
when S24 =>
q <= "11000";
NEXT_STATE <= S25;
when S25 =>
q <= "11001";
NEXT_STATE <= S26;
when S26 =>
q <= "11010";
NEXT_STATE <= S27;
when S27 =>
q <= "11011";
NEXT_STATE <= S28;
when S28 =>
q <= "11100";
NEXT_STATE <= S29;
when S29 =>
q <= "11101";
NEXT_STATE <= S30;
when S30 =>
q <= "11110";
NEXT_STATE <= S31;
when S31 =>
q <= "11111";
NEXT_STATE <= S0;
when OTHERS =>
assert ( '1' )
report "Illegal State";
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '1') and not (clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
/kontrol_kuncix.fsm
0,0 → 1,183
--Nama file : kontrol_kuncix.fsm
--Deskripsi : kontrol pembangkitan (pengaturan) kunci
--Author : Mas Adit
--Tanggal : 24 Agustus 2001
 
entity kontrol_kuncix is
port (
clk : in bit;
start : in bit;
rst : in bit;
f_enkey : in bit;
f_invmul : in bit;
f_invadd : in bit;
rst_all : out bit;
key_ready : out bit;
s_enkey : out bit;
s_invmul : out bit;
s_invadd : out bit;
vdd : in bit;
vss : in bit
);
end kontrol_kuncix;
 
architecture STATE_MACHINE of kontrol_kuncix is
 
type STATE_TYPE is (S0, S2, S3, S4, S5, S6, S7, S8, S9);
--pragma CLOCK clk
--pragma CURRENT_STATE CURRENT_STATE
--pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
 
begin
 
process (CURRENT_STATE, rst, start, f_enkey, f_invmul, f_invadd)
begin
if (rst = '1') then
NEXT_STATE <= S0;
rst_all <= '1';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '0';
else
 
 
case CURRENT_STATE is
 
when S0 =>
if (start = '1') then
if (f_enkey = '0') then
NEXT_STATE <= S3;
rst_all <= '0';
s_enkey <= '1';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '0';
else
NEXT_STATE <= S2;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '0';
end if;
else
NEXT_STATE <= S0;
rst_all <= '1';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '0';
end if;
when S3 =>
NEXT_STATE <= S0;
rst_all <= '1';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '0';
when S2 =>
if (f_invmul = '0') then
NEXT_STATE <= S4;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='1';
key_ready <= '0';
s_invadd <= '0';
else
NEXT_STATE <= S5;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '0';
end if;
when S4 =>
if (f_invadd = '0') then
NEXT_STATE <= S6;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='1';
key_ready <= '0';
s_invadd <= '1';
else
NEXT_STATE <= S7;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='1';
key_ready <= '0';
s_invadd <= '0';
end if;
when S5 =>
if (f_invadd = '0') then
NEXT_STATE <= S8;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '1';
else
NEXT_STATE <= S9;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '1';
s_invadd <= '0';
end if;
 
 
 
when S6 =>
NEXT_STATE <= S6;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='1';
key_ready <= '0';
s_invadd <= '1';
 
when S7 =>
NEXT_STATE <= S7;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='1';
key_ready <= '0';
s_invadd <= '0';
 
when S8 =>
NEXT_STATE <= S8;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '0';
s_invadd <= '1';
 
when S9 =>
NEXT_STATE <= S9;
rst_all <= '0';
s_enkey <= '0';
s_invmul <='0';
key_ready <= '1';
s_invadd <= '0';
 
end case;
end if;
end process;
 
process (clk)
begin
if ((clk = '0') and not(clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
 
end STATE_MACHINE;
 
 
 
 
 
 
 
 
 

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