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URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

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    /instruction_list_pipelined_processor_with_peripherals/trunk/hdl
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Rev 11 → Rev 12

/tb.v File deleted
/spiStatReg.v File deleted
/spi_top.v File deleted
/spiConReg.v File deleted
/spiBufReg.v File deleted
/spiEngine.v File deleted
/defines.v
76,10 → 76,10
`define UARTrd `instOpCodeLen'b10110
`define UARTwr `instOpCodeLen'b10111
`define UARTstat `instOpCodeLen'b11000
`define SPIxFER `instOpCodeLen'b11001
`define SPIstat `instOpCodeLen'b11010
`define SPIwBUF `instOpCodeLen'b11011
`define SPIrBUF `instOpCodeLen'b11100
//`define SPIxFER `instOpCodeLen'b11001
//`define SPIstat `instOpCodeLen'b11010
//`define SPIwBUF `instOpCodeLen'b11011
//`define SPIrBUF `instOpCodeLen'b11100
 
// alu opcodes
`define aluOpcodeLen 4
122,8 → 122,6
`define accMuxSelTcAcc `accMuxSelLen'b11
`define accMuxSelUartData `accMuxSelLen'b100
`define accMuxSelUartStat `accMuxSelLen'b101
`define accMuxSelSpiStat `accMuxSelLen'b110
`define accMuxSelSpiBuf `accMuxSelLen'b111
 
// operand2 multiplexer
`define op2MuxSelLen 4 // 2^4 = 16 selections available for op2
140,7 → 138,6
// peripheral defines
`define timerAndCounter_peripheral
`define UART_peripheral
`define SPI_peripheral
 
 
//-----------------------------------------------------------------------------------------------------
/accumulator.v
51,7 → 51,7
reg [7:0] accOut;
 
always @ (accEn)
always @ (posedge accEn)
begin
if (accEn)
begin
/tcAccum.v
54,7 → 54,7
reg [`tcAccLen-1:0] tcAccumOut;
always @ (tcAccumRead or tcAddr)
always @ (posedge tcAccumRead)
begin
if (tcAccumRead)
begin
/accMUX.v
49,9 → 49,6
`ifdef UART_peripheral
, uartDataIn, uartStatIn
`endif
`ifdef SPI_peripheral
, spiStatIn, spiBufIn
`endif
, accMuxOut
);
 
64,9 → 61,6
`ifdef UART_peripheral
input [7:0] uartDataIn, uartStatIn;
`endif
`ifdef SPI_peripheral
input [7:0] spiStatIn, spiBufIn;
`endif
output [7:0] accMuxOut;
106,17 → 100,8
end
`endif
`ifdef SPI_peripheral
`accMuxSelSpiStat : begin
accMuxOut = spiStatIn;
end
`accMuxSelSpiBuf : begin
accMuxOut = spiBufIn;
end
`endif
default : begin
accMuxOut = 8'bzzzzzzzz;
end
/controlUnit.v
42,33 → 42,29
`include "defines.v"
 
 
module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
branch,
module controlUnit (clk, reset, instOpCode,
iomemCode,
accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,
bitRamEn, bitRamRw, byteRamEn, byteRamRw,
inputRead, outputRw
outputRw
`ifdef timerAndCounter_peripheral
, entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn
, entypeEn, tcAccRead, tcResetEn, tcPresetEn
`endif
`ifdef UART_peripheral
, uartRead, uartWrite
`endif
`ifdef SPI_peripheral
, sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift
`endif
);
input clk, reset;
input [`instOpCodeLen-1:0] instOpCode;
input acc0;
// input acc0;
input [1:0] iomemCode;
output branch;
// output branch;
output [`accMuxSelLen-1:0] accMuxSel;
output accEn;
output [`op2MuxSelLen-1:0] op2MuxSel;
75,10 → 71,10
output aluEn;
output [`aluOpcodeLen-1:0] aluOpcode;
output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
output inputRead, outputRw;
output outputRw;
`ifdef timerAndCounter_peripheral
output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
output entypeEn, tcAccRead, tcResetEn, tcPresetEn;
`endif
`ifdef UART_peripheral
85,11 → 81,8
output uartRead, uartWrite;
`endif
`ifdef SPI_peripheral
output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
`endif
 
reg branch;
// reg branch;
reg [`accMuxSelLen-1:0] accMuxSel;
reg accEn;
reg [`op2MuxSelLen-1:0] op2MuxSel;
96,10 → 89,10
reg aluEn;
reg [`aluOpcodeLen-1:0] aluOpcode;
reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
reg inputRead, outputRw;
reg outputRw;
`ifdef timerAndCounter_peripheral
reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
reg entypeEn, tcAccRead, tcResetEn, tcPresetEn;
`endif
`ifdef UART_peripheral
106,9 → 99,6
reg uartRead, uartWrite;
`endif
`ifdef SPI_peripheral
reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
`endif
reg [`cuStateLen-1:0] state;
116,12 → 106,10
parameter s = `cuStateLen'b0;
parameter sTc = `cuStateLen'b1;
parameter sBr = `cuStateLen'b10;
parameter sLd = `cuStateLen'b11;
parameter sSt = `cuStateLen'b100;
parameter sUart = `cuStateLen'b101;
parameter sSpi = `cuStateLen'b110;
parameter sAlu = `cuStateLen'b111;
parameter sLd = `cuStateLen'b10;
parameter sSt = `cuStateLen'b11;
parameter sUart = `cuStateLen'b100;
parameter sAlu = `cuStateLen'b101;
134,11 → 122,11
begin
state = s;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluEn = 0; aluOpcode = 0; bitRamEn = 0;
bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluEn = 0; aluOpcode = 0; bitRamEn = 0;
bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0;
`endif
`ifdef UART_peripheral
145,9 → 133,6
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
else
164,9 → 149,8
`END : begin
state = sBr;
state = s;
branch = 1; // branch to some address . . .
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
176,11 → 160,10
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0;
`endif
`ifdef UART_peripheral
187,11 → 170,7
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0;
spiBufShift = 0;
`endif
end // end case END
 
 
198,12 → 177,8
 
`JMP : begin
state = sBr;
state = s;
if (acc0)
branch = 1; // branch to some address . . .
else
branch = 0;
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
213,11 → 188,10
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0;
`endif
`ifdef UART_peripheral
224,10 → 198,7
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end // end case JMP
 
 
236,7 → 207,6
// load thr. op2 MUX and alu.... enable acc in next cycle
state = sAlu;
branch = 0;
// accMuxSel = `accMuxSelAluOut;
accMuxSel = 0;
accEn = 0;
255,11 → 225,10
bitRamRw = 1'b1;
byteRamEn = 1'b1;
byteRamRw = 1'b1;
inputRead = 1'b1;
outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
266,10 → 235,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end // end case Ld
278,7 → 244,6
`Ldi : begin
state = sLd;
branch = 1'b0;
accMuxSel = `accMuxSelImmData; // select imm data thr mux
accEn = 1'b1; // acc enabled
op2MuxSel = 1'b0;
288,11 → 253,10
bitRamRw = 1'b1;
byteRamEn = 1'b0;
byteRamRw = 1'b1;
inputRead = 1'b0;
outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
299,10 → 263,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end // end case Ldi
310,14 → 271,12
`ST : begin
state = sSt;
branch = 1'b0;
accMuxSel = 1'b0;
accEn = 1'b0;
op2MuxSel = 1'b0;
aluEn = 1'b0;
aluOpcode = 1'b0;
inputRead = 1'b0;
 
case (iomemCode)
2'b10 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end
2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end
326,7 → 285,7
endcase
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
333,10 → 292,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
 
end
345,11 → 301,11
state = sAlu;
aluOpcode = `ADD_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
356,10 → 312,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
367,11 → 320,11
state = sAlu;
aluOpcode = `SUB_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
378,10 → 331,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
// MUL & DIV are not implemented
392,11 → 342,11
state = sAlu;
aluOpcode = `AND_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
403,10 → 353,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
415,11 → 362,11
state = sAlu;
aluOpcode = `OR_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
426,10 → 373,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
 
438,11 → 382,11
state = sAlu;
aluOpcode = `XOR_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
449,10 → 393,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
 
461,11 → 402,11
state = sAlu;
aluOpcode = `GT_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
472,10 → 413,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
486,11 → 424,11
state = sAlu;
aluOpcode = `GE_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
497,10 → 435,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
511,11 → 446,11
state = sAlu;
aluOpcode = `EQ_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
522,10 → 457,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
536,11 → 468,11
state = sAlu;
aluOpcode = `LE_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
547,10 → 479,7
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
561,11 → 490,11
state = sAlu;
aluOpcode = `LT_alu;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef UART_peripheral
572,44 → 501,35
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`ifdef timeAndCounter_peripheral
`PRE : begin
state = sTc;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b1; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef UART_peripheral
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
`ifdef timeAndCounter_peripheral
`ETY : begin
state = sTc;
entypeEn = 1'b1; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b1; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef UART_peripheral
616,23 → 536,18
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
`ifdef timeAndCounter_peripheral
`RST : begin
state = sTc;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b1; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b1; tcPresetEn = 1'b0;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef UART_peripheral
639,24 → 554,19
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
`ifdef timeAndCounter_peripheral
`LdTC : begin
state = sTc;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b1;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
accMuxSel = `accMuxSelTcLoad; accEn = 1'b1; // loading TC status data
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef UART_peripheral
663,24 → 573,19
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
`ifdef timeAndCounter_peripheral
`LdACC : begin
state = sTc;
entypeEn = 1'b0; tcAccRead = 1'b1; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b1; tcResetEn = 1'b0; tcPresetEn = 1'b0;
accMuxSel = `accMuxSelTcAcc; accEn = 1'b1; // loading TC ACC data
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef UART_peripheral
687,16 → 592,11
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
 
`ifdef UART_peripheral
`UARTrd : begin
state = sUart;
704,23 → 604,17
accMuxSel = `accMuxSelUartData; accEn = 1'b1; // loading UART data
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
`ifdef UART_peripheral
`UARTstat : begin
state = sUart;
728,136 → 622,33
accMuxSel = `accMuxSelUartStat; accEn = 1'b1; // loading UART status
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluOpcode = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
 
`ifdef UART_peripheral
`UARTwr : begin
state = sUart;
uartRead = 1'b0; uartWrite = 1'b1;
aluEn = 1'b0; aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
aluEn = 1'b0; aluEn = 1'b0; aluOpcode = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
 
`ifdef SPI_peripheral
`SPIxFER : begin
state = sSpi;
sconEn = 1'b1; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
`endif
 
 
 
`ifdef SPI_peripheral
`SPIstat : begin
state = sSpi;
sconEn = 1'b0; spiStatRead = 1'b1; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
`endif
 
 
 
`ifdef SPI_peripheral
`SPIwBUF : begin
state = sSpi;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b1; spiBufShift = 1'b0;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
`endif
 
 
 
`ifdef SPI_peripheral
`SPIrBUF : begin
state = sSpi;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b1; spiBufWrite = 1'b0; spiBufShift = 1'b0;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
`endif
 
default : begin
$write ("\n", $time, "ns unknown/unused instruction op-code encountered by control unit");
870,12 → 661,7
end // end case (s)
sBr : begin
branch = 1'b0;
state = s;
end // end case sBr
sLd : begin
accEn = 1'b0;
state = s;
893,26 → 679,16
state = s;
end
`ifdef timerAndCounter_peripheral
sTc : begin
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0;
state = s;
end
`endif
 
`ifdef UART_peripheral
sUart : begin
uartRead = 1'b0; uartWrite = 1'b0;
state = s;
end
`endif
 
`ifdef SPI_peripheral
sSpi : begin
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
state = s;
end
`endif
default : begin
$write (" control unit FSM in unknown state. ");
/tcPreset.v
53,7 → 53,7
reg [`tcPresetLen-1:0] presets [`tcNumbers-1:0];
always @ *
always @ (posedge tcPresetEn)
begin
if (tcPresetEn)
begin
/outputReg.v
49,10 → 49,10
input outputWriteIn;
output outputReadOut;
output [`outputNumber-1:0] outputs;
output wire [`outputNumber-1:0] outputs;
reg outputReadOut;
reg [`outputNumber-1:0] outputs = 0;
// reg [`outputNumber-1:0] outputs = 0;
reg [`outputNumber-1 :0] outputReg = 0;
69,8 → 69,6
else
begin
outputs = outputReg;
if (outputRw) // read output status
begin
outputReadOut = outputReg[outputRwAddr];
79,12 → 77,14
else // write operation
begin
outputReg[outputRwAddr] = outputWriteIn;
// $write ("\nwriting to the output register : module outputRegister ");
$write ("\nwriting to the output register : module outputRegister ");
end
end
end
assign outputs = outputReg;
 
 
endmodule
/ppReg2.v
43,13 → 43,12
 
 
module ppReg2 (clk,
branchIn,
accMuxSelIn, accEnIn, op2MuxSelIn, aluEnIn, aluOpcodeIn,
bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn,
inputReadIn, outputRwIn
outputRwIn
`ifdef timerAndCounter_peripheral
, entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn, tcLoadEnIn
, entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn
`endif
`ifdef UART_peripheral
56,17 → 55,13
, uartReadIn, uartWriteIn
`endif
`ifdef SPI_peripheral
, sconEnIn, spiStatReadIn, spiBufReadIn, spiBufWriteIn, spiBufShiftIn
`endif
, fieldIn
, branchOut,
accMuxSelOut, accEnOut, op2MuxSelOut, aluEnOut, aluOpcodeOut,
, accMuxSelOut, accEnOut, op2MuxSelOut, aluEnOut, aluOpcodeOut,
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
inputReadOut, outputRwOut
outputRwOut
`ifdef timerAndCounter_peripheral
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut
`endif
`ifdef UART_peripheral
73,16 → 68,11
, uartReadOut, uartWriteOut
`endif
`ifdef SPI_peripheral
, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
`endif
, fieldOut
);
 
input clk;
input branchIn;
input [`accMuxSelLen-1:0] accMuxSelIn;
input accEnIn;
input [`op2MuxSelLen-1:0] op2MuxSelIn;
89,20 → 79,16
input aluEnIn;
input [`aluOpcodeLen-1:0] aluOpcodeIn;
input bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn;
input inputReadIn, outputRwIn;
input outputRwIn;
`ifdef timerAndCounter_peripheral
input entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn, tcLoadEnIn;
input entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn;
`endif
`ifdef UART_peripheral
input uartReadIn, uartWriteIn;
`endif
`ifdef SPI_peripheral
input sconEnIn, spiStatReadIn, spiBufReadIn, spiBufWriteIn, spiBufShiftIn;
`endif
input [`instFieldLen-1:0] fieldIn;
 
output branchOut;
output [`accMuxSelLen-1:0] accMuxSelOut;
output accEnOut;
output [`op2MuxSelLen-1:0] op2MuxSelOut;
109,20 → 95,16
output aluEnOut;
output [`aluOpcodeLen-1:0] aluOpcodeOut;
output bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
output inputReadOut, outputRwOut;
output outputRwOut;
`ifdef timerAndCounter_peripheral
output entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
output entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
`endif
`ifdef UART_peripheral
output uartReadOut, uartWriteOut;
`endif
`ifdef SPI_peripheral
output sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
`endif
output [`instFieldLen-1:0] fieldOut;
reg branchOut;
reg [`accMuxSelLen-1:0] accMuxSelOut;
reg accEnOut;
reg [`op2MuxSelLen-1:0] op2MuxSelOut;
129,16 → 111,13
reg aluEnOut;
reg [`aluOpcodeLen-1:0] aluOpcodeOut;
reg bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
reg inputReadOut, outputRwOut;
reg outputRwOut;
`ifdef timerAndCounter_peripheral
reg entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
reg entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
`endif
`ifdef UART_peripheral
reg uartReadOut, uartWriteOut;
`endif
`ifdef SPI_peripheral
reg sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
`endif
 
reg [`instFieldLen-1:0] fieldOut;
 
149,7 → 128,6
fieldOut = fieldIn;
branchOut = branchIn;
accMuxSelOut = accMuxSelIn;
accEnOut = accEnIn;
op2MuxSelOut = op2MuxSelIn;
159,7 → 137,6
bitRamRwOut = bitRamRwIn;
byteRamEnOut = byteRamEnIn;
byteRamRwOut = byteRamRwIn;
inputReadOut = inputReadIn;
outputRwOut = outputRwIn;
`ifdef timerAndCounter_peripheral
168,8 → 145,7
tcAccReadOut = tcAccReadIn;
tcResetEnOut = tcResetEnIn;
tcPresetEnOut = tcPresetEnIn;
tcLoadEnOut = tcLoadEnIn;
 
`endif
 
 
180,17 → 156,7
 
`endif
 
 
`ifdef SPI_peripheral
sconEnOut = sconEnIn;
spiStatReadOut = spiStatReadIn;
spiBufReadOut = spiBufReadIn;
spiBufWriteOut = spiBufWriteIn;
spiBufShiftOut = spiBufShiftIn;
`endif
end
 
 
/top.v
47,10 → 47,6
, rx, tx
`endif
`ifdef SPI_peripheral
, MISO, MOSI, SCK
`endif
);
 
 
62,12 → 58,8
input rx;
output tx;
`endif
`ifdef SPI_peripheral
input MISO;
output MOSI, SCK;
`endif
 
 
// wires (interconnects) of execution unit
 
wire [`instAddrLen-1:0] pcOut;
92,9 → 84,9
wire aluEnc;
wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
wire inputReadOutc, outputRwOutc;
wire outputRwOutc;
`ifdef timerAndCounter_peripheral
wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc;
`endif
`ifdef UART_peripheral
wire uartReadOutc, uartWriteOutc;
101,9 → 93,6
wire [7:0] uartDataOut;
wire rxEmpty, txFull;
`endif
`ifdef SPI_peripheral
wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
`endif
 
wire branchOut;
wire [`accMuxSelLen-1:0] accMuxSelOut;
112,17 → 101,13
wire aluEn;
wire [`aluOpcodeLen-1:0] aluOpcodeOut;
wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
wire inputReadOut, outputRwOut;
wire outputRwOut;
`ifdef timerAndCounter_peripheral
wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
`endif
`ifdef UART_peripheral
wire uartReadOut, uartWriteOut;
`endif
`ifdef SPI_peripheral
wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
`endif
 
// wires (interconnects) of timer & counter
140,12 → 125,7
 
`endif
 
`ifdef SPI_peripheral
 
wire [7:0] spiStatOut, spiBufOut;
`endif
 
 
wire clk_d, clk_t;
reg [10:0] cnt = 0;
198,19 → 178,15
 
//-------- Control Unit Module Instance
 
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
branchOutc,
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, instField2[8:7],
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc
`ifdef timerAndCounter_peripheral
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc
`endif
`ifdef UART_peripheral
, uartReadOutc, uartWriteOutcc
`endif
`ifdef SPI_peripheral
, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
`endif
);
 
221,27 → 197,22
 
ppReg2 PipeLine_Reg2 (clk,
branchOutc,
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc
`ifdef timerAndCounter_peripheral
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc
`endif
`ifdef UART_peripheral
, uartReadOutc, uartWriteOutcc
`endif
`ifdef SPI_peripheral
, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
`endif
, instField1
, branchOut,
accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
,accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
inputReadOut, outputRwOut
outputRwOut
`ifdef timerAndCounter_peripheral
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut
`endif
`ifdef UART_peripheral
248,10 → 219,6
, uartReadOut, uartWriteOut
`endif
`ifdef SPI_peripheral
, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
`endif
, instField2
);
 
269,9 → 236,6
`ifdef UART_peripheral
, uartDataOut, {rxEmpty, txFull}
`endif
`ifdef SPI_peripheral
, spiStatOut, spiBufOut
`endif
, accMuxOut
);
 
313,17 → 277,15
`ifdef timerAndCounter_peripheral
 
 
 
 
tcEnableAndType tcEnableAndTypeModule(entypeEnOut, accOut[0], instField2[5:4], instField2[3:0], enWires, typeWires);
tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
tcReset tcResetModule(tcResetEnOut, accOut[0], instField2[3:0], resetWires);
tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
tcLoad tcLoadModule(instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
366,15 → 328,4
 
`endif
 
//---------- SPI Modules
// optional
 
`ifdef SPI_peripheral
 
 
spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
 
 
`endif
endmodule
/tcEnableAndType.v
54,7 → 54,7
reg enables [`tcNumbers-1:0];
reg [`tcTypeLen-1:0] types [`tcNumbers-1:0];
always @ *
always @ (posedge entypeEn)
begin
if (entypeEn)
begin
/tcLoad.v
42,31 → 42,23
`include "defines.v"
 
 
module tcLoad (tcLoadEn, tcAddr, dnIn, ttIn, cuIn, cdIn, tcLoadOut);
module tcLoad (tcAddr, dnIn, ttIn, cuIn, cdIn, tcLoadOut);
 
input tcLoadEn;
input [`tcAddrLen-1:0] tcAddr;
input [`tcNumbers-1:0] dnIn, ttIn, cuIn, cdIn;
output [7:0] tcLoadOut;
reg [`tcNumbers-1:0] dnInReg, ttInReg, cuInReg, cdInReg;
wire dnSel, ttSel, cuSel, cdSel;
always @ *
begin
dnInReg = dnIn;
ttInReg = ttIn;
cuInReg = cuIn;
cdInReg = cdIn;
end
assign dnSel = dnInReg[tcAddr];
assign ttSel = ttInReg[tcAddr];
assign cuSel = cuInReg[tcAddr];
assign cdSel = cdInReg[tcAddr];
assign dnSel = dnIn[tcAddr];
assign ttSel = ttIn[tcAddr];
assign cuSel = cuIn[tcAddr];
assign cdSel = cdIn[tcAddr];
 
assign tcLoadOut = {4'b0, dnSel, ttSel, cuSel, cdSel};
assign tcLoadOut = {4'b0, cdSel, cuSel, ttSel, dnSel};
 
 
endmodule
/tcReset.v
52,7 → 52,7
reg [`tcNumbers-1:0] resets;
always @ *
always @ (posedge tcResetEn)
begin
if (tcResetEn)
begin

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