URL
https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
Subversion Repositories instruction_list_pipelined_processor_with_peripherals
Compare Revisions
- This comparison shows the changes necessary to convert path
/instruction_list_pipelined_processor_with_peripherals/trunk
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/program_rom/romCreate.plx
217,13 → 217,11
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr; |
}; |
case ETY { |
print "\nAssert (1) or De-assert (0) enable signal?\t"; |
my $resp = <STDIN>; chop($resp); |
print "\nTimer or Counter Type :\t 00 = on-delayTimer, 01 = off-delayTimer, 10 = retOn-delayTimer\n\t\t\t01 = up-counter, 10 = down-counter\n\t\t"; |
my $resp2 = <STDIN>; chop($resp2); |
my $addr = sub2(); my $zero = 0; |
|
$fld = $zero.$zero.$zero.$resp.$resp2.$addr; |
$fld = $zero.$zero.$zero.$zero.$resp2.$addr; |
}; |
case RST { |
print "\nAssert (1) or De-assert (0) Reset signal?\t"; |
/doc/inst_set_documet_rev_1_12042014.doc
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doc/inst_set_documet_rev_1_12042014.doc
Property changes :
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Index: doc/inst_set_documet_rev_2_09062014.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: doc/inst_set_documet_rev_2_09062014.doc
===================================================================
--- doc/inst_set_documet_rev_2_09062014.doc (nonexistent)
+++ doc/inst_set_documet_rev_2_09062014.doc (revision 11)
doc/inst_set_documet_rev_2_09062014.doc
Property changes :
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Index: hdl/top.v
===================================================================
--- hdl/top.v (revision 10)
+++ hdl/top.v (revision 11)
@@ -300,8 +300,12 @@
inputRegister inputStorage (IN, instField2[6:0], inputReadOutData);
- outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
+ wire outIn;
+ bitNegator bitNegatorForOutReg (accOut[0], instField2[9], outIn);
+
+ outputReg outputStorage (reset, outputRwOut, instField2[6:0], outIn, outputReadOut, OUT);
+
//---------- Timer & Counter Modules
// optional
@@ -311,7 +315,7 @@
- tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
+ tcEnableAndType tcEnableAndTypeModule(entypeEnOut, accOut[0], instField2[5:4], instField2[3:0], enWires, typeWires);
tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
/hdl/alu.v
41,10 → 41,17
`include "timescale.v" |
`include "defines.v" |
|
module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn, |
output [7:0] aluOut, output carryOut); |
module alu (aluOpcode, op1, op2, aluEn, aluOut, carryOut); |
|
|
input [`aluOpcodeLen-1:0] aluOpcode; |
input [7:0] op1; |
input [7:0] op2; |
input aluEn; |
|
output [7:0] aluOut; |
output carryOut; |
|
wire [8:0] operand1 = {1'b0, op1}; |
wire [8:0] operand2 = {1'b0, op2}; |
|
51,7 → 58,7
wire [8:0] addRes = operand1 + operand2; |
wire [8:0] subRes = operand1 - operand2; |
|
reg [8:0] aluOut = 0; |
reg [7:0] aluOut = 0; |
reg carryOut = 0; |
|
always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode) |