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Rev 4 → Rev 5

/hdl/onDelayTimer.v File deleted
/hdl/defines.v
1,4 → 1,5
// 16-bit process controller defines
// 16-bit process controller defines
 
`define immDataLen 8
 
7,6 → 8,38
`define instOpCodeLen 5
`define instFieldLen 10
 
 
// control unit
`define cuStateLen 4 // max 16 states
`define END `instOpCodeLen'b0
`define JMP `instOpCodeLen'b1
`define Ld `instOpCodeLen'b10
`define Ldi `instOpCodeLen'b11
`define ST `instOpCodeLen'b100
`define ADD `instOpCodeLen'b101
`define SUB `instOpCodeLen'b110
`define MUL `instOpCodeLen'b111
`define DIV `instOpCodeLen'b1000
`define AND `instOpCodeLen'b1001
`define OR `instOpCodeLen'b1010
`define XOR `instOpCodeLen'b1011
`define GrT `instOpCodeLen'b1100
`define GE `instOpCodeLen'b1101
`define EQ `instOpCodeLen'b1110
`define LE `instOpCodeLen'b1111
`define LT `instOpCodeLen'b10000
`define PRE `instOpCodeLen'b10001
`define ETY `instOpCodeLen'b10010
`define RST `instOpCodeLen'b10011
`define LdTC `instOpCodeLen'b10100
`define LdACC `instOpCodeLen'b10101
`define UARTrd `instOpCodeLen'b10110
`define UARTwr `instOpCodeLen'b10111
`define SPIxFER `instOpCodeLen'b11000
`define SPIstat `instOpCodeLen'b11001
`define SPIwBUF `instOpCodeLen'b11010
`define SPIrBUF `instOpCodeLen'b11011
 
// alu opcodes
`define aluOpcodeLen 4
`define AND_alu `aluOpcodeLen'b0
21,8 → 54,8
`define SUB_alu `aluOpcodeLen'b1001
`define MUL_alu `aluOpcodeLen'b1010
`define DIV_alu `aluOpcodeLen'b1011
`define LD_data `aluOpcodeLen'b1100
 
 
// bit RAM
`define bitRamAddrLen 7 // 7-bit address
`define bitRamDepth 128 // 2^7 = 128 locations
41,20 → 74,21
`define outputAddrLen 7 // 7-bit address
 
// accumulator multiplexer
`define accMuxSelLen 4 // 2^4 = 16 selections available for accumulator
`define accMuxSel0 `accMuxSelLen'b0
`define accMuxSel1 `accMuxSelLen'b1
`define accMuxSel2 `accMuxSelLen'b10
`define accMuxSel3 `accMuxSelLen'b11
`define accMuxSel4 `accMuxSelLen'b100
`define accMuxSel5 `accMuxSelLen'b101
`define accMuxSelLen 4 // 2^4 = 16 selections available for accumulator
`define accMuxSelImmData `accMuxSelLen'b0
`define accMuxSelAluOut `accMuxSelLen'b1
`define accMuxSelTcLoad `accMuxSelLen'b10
`define accMuxSelTcAcc `accMuxSelLen'b11
`define accMuxSelUart `accMuxSelLen'b100
`define accMuxSelSpiStat `accMuxSelLen'b101
`define accMuxSelSpiBuf `accMuxSelLen'b110
 
// operand2 multiplexer
`define op2MuxSelLen 4 // 2^4 = 16 selections available for op2
`define op2MuxSel0 `op2MuxSelLen'b0
`define op2MuxSel1 `op2MuxSelLen'b1
`define op2MuxSel2 `op2MuxSelLen'b10
`define op2MuxSel3 `op2MuxSelLen'b11
`define op2MuxSelLen 4 // 2^4 = 16 selections available for op2
`define op2MuxSelInput `op2MuxSelLen'b0
`define op2MuxSelOutput `op2MuxSelLen'b1
`define op2MuxSelBitRam `op2MuxSelLen'b10
`define op2MuxSelByteRam `op2MuxSelLen'b11
`define op2MuxSel4 `op2MuxSelLen'b100
`define op2MuxSel5 `op2MuxSelLen'b101
`define op2MuxSel6 `op2MuxSelLen'b110
64,7 → 98,7
// peripheral defines
`define timerAndCounter_peripheral
`define UART_peripheral
`define SPI_peripheral
//`define SPI_peripheral
 
 
//-----------------------------------------------------------------------------------------------------
/hdl/controlUnit.v
3,7 → 3,7
`include "defines.v"
 
 
module controlUnit (clk, reset, instOpCodeIn, acc0, iomemCode,
module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
branch,
accMuxSel, accEn, op2MuxSel, aluOpcode,
bitRamEn, bitRamRw, byteRamEn, byteRamRw,
39,7 → 39,7
`ifdef timerAndCounter_peripheral
output entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
`endif;
`endif
`ifdef UART_peripheral
output uartRead, uartWrite;
48,8 → 48,809
`ifdef SPI_peripheral
output sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
`endif
 
reg branch;
reg [`accMuxSelLen-1:0] accMuxSel;
reg accEn;
reg [`op2MuxSelLen-1:0] op2MuxSel;
reg [`aluOpcodeLen-1:0] aluOpcode;
reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
reg inputRead, outputRw;
`ifdef timerAndCounter_peripheral
reg entypeEn, tcAccRead, tcResetEn, tcPresetEn, tcLoadEn;
`endif
`ifdef UART_peripheral
reg uartRead, uartWrite;
`endif
`ifdef SPI_peripheral
reg sconEn, spiStatRead, spiBufRead, spiBufWrite, spiBufShift;
`endif
reg [`cuStateLen-1:0] state;
// control unit FSM states:
parameter s = `cuStateLen'b0;
parameter sTc = `cuStateLen'b1;
parameter sBr = `cuStateLen'b10;
parameter sLd = `cuStateLen'b11;
parameter sSt = `cuStateLen'b100;
parameter sUart = `cuStateLen'b101;
parameter sSpi = `cuStateLen'b110;
parameter sAlu = `cuStateLen'b111;
always @ (negedge clk)
begin
if (reset)
begin
state = s;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluOpcode = 0; bitRamEn = 0;
bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
else
begin
// execution unit control signals
case (state)
s : begin
 
case (instOpCode)
`END : begin
state = sBr;
branch = 1; // branch to some address . . .
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluOpcode = 0;
bitRamEn = 0;
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0;
spiBufShift = 0;
`endif
end // end case END
 
 
 
`JMP : begin
state = sBr;
branch = 1; // branch to some address . . .
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluOpcode = 0;
bitRamEn = 0;
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end // end case JMP
 
 
 
`Ld : begin
// load thr. op2 MUX and alu.... enable acc in next cycle
state = sLd;
branch = 0;
accMuxSel = 0;
accEn = 0;
case (iomemCode)
2'b00 : op2MuxSel = `op2MuxSelInput;
2'b01 : op2MuxSel = `op2MuxSelOutput;
2'b10 : op2MuxSel = `op2MuxSelBitRam;
2'b11 : op2MuxSel = `op2MuxSelByteRam;
default: op2MuxSel = `op2MuxSelInput;
endcase
aluOpcode = `LD_data;
bitRamEn = 0;
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end // end case Ld
`Ldi : begin
state = sAlu;
branch = 0;
accMuxSel = `accMuxSelImmData; // select imm data thr mux
accEn = 1; // acc enabled
op2MuxSel = 0;
aluOpcode = 0;
bitRamEn = 0;
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end // end case Ldi
`ST : begin
state = sSt;
branch = 0;
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluOpcode = 0;
bitRamRw = 0;
byteRamRw = 0;
inputRead = 0;
 
case (iomemCode)
2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; end
2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; end
2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
endcase
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
 
end
`ADD : begin
state = sAlu;
aluOpcode = `ADD_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`SUB : begin
state = sAlu;
aluOpcode = `SUB_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
// MUL & DIV are not implemented
`AND : begin
state = sAlu;
aluOpcode = `AND_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`OR : begin
state = sAlu;
aluOpcode = `OR_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
 
 
`XOR : begin
state = sAlu;
aluOpcode = `XOR_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
 
 
`GrT : begin
state = sAlu;
aluOpcode = `GT_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
 
 
`GE : begin
state = sAlu;
aluOpcode = `GE_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
 
 
`EQ : begin
state = sAlu;
aluOpcode = `EQ_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
 
 
`LE : begin
state = sAlu;
aluOpcode = `LE_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
 
 
`LT : begin
state = sAlu;
aluOpcode = `LT_alu;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`ifdef timeAndCounter_peripheral
`PRE : begin
state = sTc;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
`ifdef timeAndCounter_peripheral
`ETY : begin
state = sTc;
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
 
 
`ifdef timeAndCounter_peripheral
`RST : begin
state = sTc;
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
 
 
`ifdef timeAndCounter_peripheral
`LdTC : begin
state = sTc;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
aluOpcode = 0; branch = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
 
 
`ifdef timeAndCounter_peripheral
`LdACC : begin
state = sTc;
entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
aluOpcode = 0; branch = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
 
 
 
`ifdef UART_peripheral
`UARTrd : begin
state = sUart;
uartRead = 1; uartWrite = 0;
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
aluOpcode = 0; branch = 0;op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
 
 
 
`ifdef UART_peripheral
`UARTwr : begin
state = sUart;
uartRead = 0; uartWrite = 1;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
`endif
end
`endif
 
 
 
 
`ifdef SPI_peripheral
`SPIxFER : begin
state = sSpi;
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
end
`endif
 
 
 
`ifdef SPI_peripheral
`SPIstat : begin
state = sSpi;
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
end
`endif
 
 
 
`ifdef SPI_peripheral
`SPIwBUF : begin
state = sSpi;
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
end
`endif
 
 
 
`ifdef SPI_peripheral
`SPIrBUF : begin
state = sSpi;
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
`endif
end
`endif
 
default : begin
$write (" unknown/unused instruction op-code encountered by control unit ");
$stop;
end
endcase // end case (instOpCode)
end // end case (s)
sBr : begin
branch = 0;
state = s;
end // end case sBr
sLd : begin
accEn = 0;
state = s;
end // end case sLd
sSt : begin
bitRamRw = 1; byteRamRw = 1; outputRw = 1;
state = s;
end
sAlu : begin
accEn = 1;
accMuxSel = `accMuxSelAluOut;
state = s;
end
`ifdef timerAndCounter_peripheral
sTc : begin
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
state = s;
end
`endif
 
`ifdef UART_peripheral
sUart : begin
uartRead = 0; uartWrite = 0;
state = s;
end
`endif
 
`ifdef SPI_peripheral
sSpi : begin
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
state = s;
end
`endif
default : begin
$write (" control unit FSM in unknown state. ");
end
endcase // end case (state)
end // end else part (outermost)
end // end always
endmodule
/hdl/accMUX.v
3,11 → 3,31
`include "defines.v"
 
 
module accumulatorMUX (accMuxSel, immData, aluOut, accMuxOut);
module accumulatorMUX (accMuxSel, immData, aluOut
`ifdef timerAndCounter_peripheral
, tcLoadIn, tcAccIn
`endif
`ifdef UART_peripheral
, uartDataIn
`endif
`ifdef SPI_peripheral
, spiStatIn, spiBufIn
`endif
, accMuxOut
);
 
input [`accMuxSelLen-1:0] accMuxSel;
input [`immDataLen-1:0] immData;
input [7:0] aluOut;
`ifdef timerAndCounter_peripheral
input [7:0] tcLoadIn, tcAccIn;
`endif
`ifdef UART_peripheral
input [7:0] uartDataIn;
`endif
`ifdef SPI_peripheral
input [7:0] spiStatIn, spiBufIn;
`endif
output [7:0] accMuxOut;
19,14 → 39,41
case (accMuxSel)
`accMuxSel0 : begin
accMuxOut = immData;
end
`accMuxSelImmData : begin
accMuxOut = immData;
end
`accMuxSel1 : begin
accMuxOut = aluOut;
end
`accMuxSelAluOut : begin
accMuxOut = aluOut;
end
`ifdef timerAndCounter_peripheral
`accMuxSelTcLoad : begin
accMuxOut = tcLoadIn;
end
`accMuxSelTcAcc : begin
accMuxOut = tcAccIn;
end
`endif
`ifdef UART_peripheral
`accMuxSelUart : begin
accMuxOut = uartDataIn;
end
`endif
`ifdef SPI_peripheral
`accMuxSelSpiStat : begin
accMuxOut = spiStatIn;
end
`accMuxSelSpiBuf : begin
accMuxOut = spiBufIn;
end
`endif
default : begin
accMuxOut = 8'bzzzzzzzz;
end
/hdl/alu.v
63,6 → 63,10
aluOutput = subRes[7:0];
carryOutput = subRes[8];
end
`LD_data : begin
aluOutput = op1;
end
default : begin
aluOutput = 16'b0;
/hdl/op2Mux.v
19,19 → 19,19
case (op2MuxSel)
`op2MuxSel0 : begin
`op2MuxSelInput : begin
op2MuxOut = {7'b0, inputReadOut};
end
`op2MuxSel1 : begin
`op2MuxSelOutput : begin
op2MuxOut = {7'b0, outputReadOut};
end
`op2MuxSel2 : begin
`op2MuxSelBitRam : begin
op2MuxOut = {7'b0, bitOut};
end
`op2MuxSel3 : begin
`op2MuxSelByteRam : begin
op2MuxOut = byteOut;
end
/hdl/top.v
32,6 → 32,7
// wires (interconnects) of execution unit
 
wire [`instLen-1:0] pcOut;
wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
wire [`instOpCodeLen-1:0] instOpCode;
wire [`instFieldLen-1:0] instField;
43,37 → 44,169
wire bitNegatorRamOut, bitOut;
wire [7:0] byteNegatorRamOut, byteOut;
wire inputReadOut, outputReadOut;
wire inputReadOutData, outputReadOut;
// wires (interconnects) of timer & counter
wire branchOutc;
wire [`accMuxSelLen-1:0] accMuxSelOutc;
wire accEnOutc;
wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
wire inputReadOutc, outputRwOutc;
`ifdef timerAndCounter_peripheral
wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
`endif
`ifdef UART_peripheral
wire uartReadOutc, uartWriteOutc;
`endif
`ifdef SPI_peripheral
wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
`endif
 
wire branchOut;
wire [`accMuxSelLen-1:0] accMuxSelOut;
wire accEnOut;
wire [`op2MuxSelLen-1:0] op2MuxSelOut;
wire [`aluOpcodeLen-1:0] aluOpcodeOut;
wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
wire inputReadOut, outputRwOut;
`ifdef timerAndCounter_peripheral
wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
`endif
`ifdef UART_peripheral
wire uartReadOut, uartWriteOut;
`endif
`ifdef SPI_peripheral
wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
`endif
 
// wires (interconnects) of timer & counter
 
`ifdef timerAndCounter_peripheral
 
wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
wire [7:0] tcAccumOut;
wire [7:0] tcLoadOut;
wire [`tcNumbers-1:0] enWires;
wire [`tcNumbers-1:0] resetWires;
wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
wire [(`tcNumbers*2)-1:0] typeWires;
wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
 
`endif
 
// wires (interconnects) of UART
 
`ifdef UART_peripheral
`endif
// wires (interconnects) of SPI
 
`ifdef SPI_peripheral
`endif
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
pgmCounter ProgramCounter ();
pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
instReg IntructionRegister ();
 
// instruction ROM is declared using xilinx primitive
RAMB16_S18 rom ( .DI(),
.DIP(),
.ADDR(),
.ADDR(pcOut),
.EN(1'b1),
.WE(),
.SSR(1'b0),
.CLK(),
.DO(),
.CLK(clk),
.DO(romOut),
.DOP());
 
instReg IntructionRegister (romOut, instOpCode, instField);
 
 
// pipeline register
 
wire [`instOpCodeLen-1:0] instOpCode1;
wire [`instFieldLen-1:0] instField1;
wire [`instFieldLen-1:0] instField2;
ppReg1 PipeLine_Reg1 (clk, instOpcode, instField, instOpcode1, instField1);
 
 
//-------- Control Unit Module Instance
 
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
branchc,
accMuxSelc, accEnc, op2MuxSelc, aluOpcodec,
bitRamEnc, bitRamRwc, byteRamEnc, byteRamRwc,
inputReadc, outputRwc
`ifdef timerAndCounter_peripheral
, entypeEnc, tcAccReadc, tcResetEnc, tcPresetEnc, tcLoadEnc
`endif
`ifdef UART_peripheral
, uartReadc, uartWritec
`endif
`ifdef SPI_peripheral
, sconEnc, spiStatReadc, spiBufReadc, spiBufWritec, spiBufShiftc
`endif
);
 
 
 
// pipeline register
 
 
ppReg2 PipeLine_Reg2 (clk,
branchOutc,
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluOpcodeOutc, bitRamEnOutc,
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
`ifdef timerAndCounter_peripheral
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
`endif
`ifdef UART_peripheral
, uartReadOutc, uartWriteOutcc
`endif
`ifdef SPI_peripheral
, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
`endif
, instField1
, branchOut,
accMuxSelOut, accEnOut, op2MuxSelOut, aluOpcodeOut,
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
inputReadOut, outputRwOut
`ifdef timerAndCounter_peripheral
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
`endif
`ifdef UART_peripheral
, uartReadOut, uartWriteOut
`endif
`ifdef SPI_peripheral
, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
`endif
, instField2
);
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
80,28 → 213,46
 
accumulatorMUX accMUX1 ();
accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut
`ifdef timerAndCounter_peripheral
, tcLoadOut, tcAccOut
`endif
`ifdef UART_peripheral
, uartDataOut
`endif
`ifdef SPI_peripheral
, spiStatOut, spiBufOut
`endif
, accMuxOut
);
 
accumulator acc ();
accumulator acc (accMuxOut, accEnOut, accOut);
 
byteNegator byteNegatorForOp2Mux ();
op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
op2Mux op2MUX1 ();
wire [7:0] op2Out;
alu arithLogicUnit ();
byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
bitNegator bitNegatorForBitRam ();
alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluOut, carryOut);
bitRam RAM_Bit ();
wire bitIn;
byteNegator byteNegatorForByteRam ();
bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);
byteRam RAM_Byte ();
bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
inputRegister inputStorage ();
wire [7:0] byteIn;
outputReg outputStorage ();
byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);
byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
 
//---------- Timer & Counter Modules
// optional
108,31 → 259,34
 
`ifdef timerAndCounter_peripheral
 
tcEnableAndType tcEnableAndTypeModule();
 
 
 
tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
tcAccum tcAccumModule();
tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
tcReset tcResetModule();
tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
tcPreset tcPresetModule();
tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
tcLoad tcLoadModule();
tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
timer timer0();
timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
timer timer1();
timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
timer timer2();
timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
timer timer3();
timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
counter counter0();
counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
counter counter1();
counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
counter counter2();
counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
counter counter3();
counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
 
`endif
 
141,17 → 295,22
 
`ifdef UART_peripheral
 
wire brgOut;
wire txDoneTick, txStart;
wire rxDoneTick;
wire [7:0] recFifoData, transFifoData;
 
uartTrans UART_TRANSMITTER ();
uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
uartRec UART_RECIEVER ();
uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
uartBrg UART_BitRateGenerator ();
uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
uartFifo UART_TRANS_FIFO ();
uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
uartFifo UART_REC_FIFO ();
uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
 
`endif
 
//---------- SPI Modules

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