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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

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Rev 8 → Rev 9

/program_rom/romCreate.plx
0,0 → 1,349
# programmer for 8-bit pipelined processor
# Mahesh Sukhdeo Palve
# 09042014
# !/usr/bin/perl
use warnings;
# use strict;
 
my $file_asm = '> C:\asm.txt';
open FILE_ASM, $file_asm or die " PROBLEM READING FILE : $! \n";
 
 
my $file_rom = '> C:\rom.v';
open FILE_V, $file_rom or die "PROBLEM READING FILE : $! \n";
 
 
print ("\n\nLast modified by : Mahesh Sukhdeo Palve");
print (" \n\n8-bit Pipeline Processor");
print (" \n\n for Open Cores (opencores.org)");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
print ("\n\n\t\tPROGRAMMER . . .\n\n");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
 
print ("\nStart entering instructions-\n");
 
# take instruction?
 
my $inst = 0;
my $addr = 0;
 
print FILE_V "`include \"defines.v\"\n`include \"timescale.v\"\n\n";
print FILE_V "\tmodule\trom (clk, addr, code);\n";
print FILE_V "\t\tinput clk;\n\t\tinput [`instAddrLen-1:0] addr; \n\t\t output [`instLen-1:0] code;\n\n";
print FILE_V "\t\treg [`instLen-1:0] code;";
print FILE_V "\n\n\n\t\t\talways @ (posedge clk)\n\t\t\tbegin\n\n";
print FILE_V "\t\t\t case (addr)";
 
 
while ($inst ne END)
{
print "\nmnemonic :\t";
$inst = <STDIN>;
chop ($inst);
my $opcode = getOpcode($inst);
# print "\nopcode for $inst is $opcode\n";
my $field = getField($inst);
# print "\nfield for $inst is $field\n";
my $instruction = $opcode.$field;
print "\n The instruction at address $addr is $instruction\n\n";
my $zero = 0;
print FILE_ASM $inst."\t\t".$field."\n";
print FILE_V "\n\t\t\t\t$addr\t:\tcode = 15'b$instruction;";
$addr = $addr + 1;
}
 
print FILE_V "\n\n\t\t\tdefault\t:\tcode = 15'b111111111111111;";
print FILE_V "\n\t\tendcase\nend\n\nendmodule\n";
 
 
 
sub bin2hex {
my $bin = shift;
 
# Make input bit string a multiple of 4
#$bin = substr("0000",length($bin)%4) . $bin if length($bin)%4;
 
my ($hex, $nybble) = ("");
while (length($bin)) {
($nybble,$bin) = (substr($bin,0,4), substr($bin,4)); # (substr($bin,0,4), substr($bin,4));
#substr extracts a substring . . .
$nybble = eval "0b$nybble";
$hex .= substr("0123456789ABCDEF", $nybble, 1);
}
return $hex;
}
 
 
 
 
 
##############
# getOpcode
 
sub getOpcode{
 
my $temp;
my $zero = 0;
my $opcod;
use Switch;
 
switch ($inst) {
 
case END { $temp = 0; $opcod = $temp.$temp.$temp.$temp.$temp;};
case JMP { $temp = 1; $opcod = $zero.$zero.$zero.$zero.$temp;};
case Ld { $temp = 10; $opcod = $zero.$zero.$zero.$temp;};
case Ldi { $temp = 11; $opcod = $zero.$zero.$zero.$temp;};
case ST { $temp = 100; $opcod = $zero.$zero.$temp;};
case ADD { $temp = 101; $opcod = $zero.$zero.$temp;};
case SUB { $temp = 110; $opcod = $zero.$zero.$temp;};
case MUL { $temp = 111; $opcod = $zero.$zero.$temp;};
case DIV { $temp = 1000; $opcod = $zero.$temp;};
case AND { $temp = 1001; $opcod = $zero.$temp;};
case OR { $temp = 1010; $opcod = $zero.$temp;};
case XOR { $temp = 1011; $opcod = $zero.$temp;};
case GT { $temp = 1100; $opcod = $zero.$temp;};
case GE { $temp = 1101; $opcod = $zero.$temp;};
case EQ { $temp = 1110; $opcod = $zero.$temp;};
case LE { $temp = 1111; $opcod = $zero.$temp;};
case LT { $opcod = 10000;};
case PRE { $opcod = 10001;};
case ETY { $opcod = 10010;};
case RST { $opcod = 10011;};
case LdTC { $opcod = 10100;};
case LdACC { $opcod = 10101;};
case UARTrd { $opcod = 10110;};
case UARTwr { $opcod = 10111;};
case UARTstat { $opcod = 11000;};
case SPIxFER { $opcod = 11001;};
case SPIstat { $opcod = 11010;};
case SPIwBUF { $opcod = 11011;};
case SPIrBUF { $opcod = 11100;}
else {print " Inserted NOP!"; $opcod = 11111;};
}
return $opcod;
 
}
 
 
 
##################
# getField
 
sub getField{
 
my $fld = 0;
use Switch;
my $zero = 0;
my $tmp;
my $response = 0;
 
my $negate = 0;
my $iomem = 0;
my $iomemaddr = 0;
 
switch ($inst){
case END{
print "\nis start address 0? Y or N\t";
$response = <STDIN>; chop($response);
if ($response eq Y){
$tmp = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
}
else{
print "\nstart address (10 bit) :\t";
$tmp = <STDIN>;
chop($tmp);
}
$fld = $tmp;
};
case JMP {
print "\n Jump to address :\t";
$fld = <STDIN>;
chop($fld);
};
case Ld {
$fld = sub1();
};
case Ldi {
print "\nImmediate Data (8-bit):\t";
$temp = <STDIN>; chop($temp);
$fld = $zero.$zero.$temp;
}
case ST {
$fld = sub1();
};
case ADD {
$fld = sub1();
};
case SUB {
$fld = sub1();
};
case MUL {
$fld = sub1();
};
case DIV {
$fld = sub1();
};
case AND {
$fld = sub1();
};
case OR {
$fld = sub1();
};
case XOR {
$fld = sub1();
};
case GT {
$fld = sub1();
};
case GE {
$fld = sub1();
};
case EQ {
$fld = sub1();
};
case LE {
$fld = sub1();
};
case LT {
$fld = sub1();
};
case PRE {
my $addr = sub2(); my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
};
case ETY {
print "\nAssert (1) or De-assert (0) enable signal?\t";
my $resp = <STDIN>; chop($resp);
print "\nTimer or Counter Type :\t 00 = on-delayTimer, 01 = off-delayTimer, 10 = retOn-delayTimer\n\t\t\t01 = up-counter, 10 = down-counter\n\t\t";
my $resp2 = <STDIN>; chop($resp2);
my $addr = sub2(); my $zero = 0;
$fld = $zero.$zero.$zero.$resp.$resp2.$addr;
};
case RST {
print "\nAssert (1) or De-assert (0) Reset signal?\t";
my $resp = <STDIN>; chop($resp);
my $zero = 0;
my $addr = sub2();
$fld = $zero.$zero.$zero.$zero.$zero.$resp.$addr;
};
case LdTC {
my $addr = sub2(); my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
};
case LdACC {
my $addr = sub2(); my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
};
case UARTrd {
my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
};
case UARTwr {
my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
};
case UARTstat{
my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
};
case SPIxFER{
print "\nEnable (1) or disable (0)?\t";
my $resp = <STDIN>; chop($resp);
print "\nShift (1) or Stop shift (0)?\t";
my $resp2 = <STDIN>; chop($resp2);
my $zero = 0;
$fld = $zero.$zero.$resp.$zero.$zero.$zero.$zero.$zero.$zero.$resp2;
}
case SPIstat{
my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
};
case SPIrBUF{
my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
};
case SPIwBUF{
my $zero = 0;
$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
}
else {
$fld = 1111111111;
};
}
return $fld;
}
 
 
sub sub1{
print "\nNegate? Y or N\t";
$response = <STDIN>; chop($response);
if ($response eq Y){ $negate = 1;}
else {$negate = 0};
print "\nInput (i) / Output (o) / bitRAM (b) / ByteRAM (B)?";
my $select = <STDIN>; chop($select);
if ($select eq i){
my $zero = 0; $iomem = $zero.$zero;
print "\ninput address :\t";
$iomemaddr = <STDIN>; chop($iomemaddr);
}
if ($select eq o){
$temp = 1; $zero = 0;
$iomem = $zero.$temp;
print "\noutput address :\t";
$iomemaddr = <STDIN>; chop($iomemaddr);
}
if ($select eq b){
$iomem = 10;
print "\nbit RAM address :\t";
$iomemaddr = <STDIN>; chop($iomemaddr);
}
if ($select eq B){
$iomem = 11;
print "\nByte RAM address :\t";
$iomemaddr = <STDIN>; chop($iomemaddr);
}
$fld = $negate.$iomem.$iomemaddr;
return $fld;
}
 
 
 
sub sub2 {
 
print "\nEnter Timer/Counter Address (4-bit):\t";
my $addrs = <STDIN>;
chop ($addrs);
return $addrs;
}
/doc/coding_rev_1_12042014.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/coding_rev_1_12042014.doc
doc/coding_rev_1_12042014.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/inst_set_documet_rev_1_12042014.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/inst_set_documet_rev_1_12042014.doc =================================================================== --- doc/inst_set_documet_rev_1_12042014.doc (nonexistent) +++ doc/inst_set_documet_rev_1_12042014.doc (revision 9)
doc/inst_set_documet_rev_1_12042014.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/info_rev_1_12042014.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/info_rev_1_12042014.doc =================================================================== --- doc/info_rev_1_12042014.doc (nonexistent) +++ doc/info_rev_1_12042014.doc (revision 9)
doc/info_rev_1_12042014.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: hdl/controlUnit.v =================================================================== --- hdl/controlUnit.v (revision 8) +++ hdl/controlUnit.v (revision 9) @@ -195,9 +195,10 @@ `Ld : begin // load thr. op2 MUX and alu.... enable acc in next cycle - state = sLd; + state = sAlu; branch = 0; +// accMuxSel = `accMuxSelAluOut; accMuxSel = 0; accEn = 0; @@ -236,7 +237,7 @@ `Ldi : begin - state = sAlu; + state = sLd; branch = 1'b0; accMuxSel = `accMuxSelImmData; // select imm data thr mux @@ -279,9 +280,9 @@ inputRead = 1'b0; case (iomemCode) - 2'b01 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end - 2'b10 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end - 2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end + 2'b10 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end + 2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end + 2'b01 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end endcase @@ -820,7 +821,7 @@ default : begin - $write ("\nunknown/unused instruction op-code encountered by control unit "); + $write ("\n", $time, "ns unknown/unused instruction op-code encountered by control unit"); // $stop; end endcase // end case (instOpCode) @@ -837,9 +838,7 @@ sLd : begin - aluEn = 1'b0; - accEn = 1'b1; - accMuxSel = `accMuxSelAluOut; + accEn = 1'b0; state = s; end // end case sLd
/hdl/top.v
128,22 → 128,24
 
//-------- Fetch Unit Module Instances
// all necessary
wire branch = (~romOut[14] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[10]) | ((romOut[10] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[14]) & accOut[0]); // END = 00000; JMP = 00001
 
pgmCounter ProgramCounter (clk_d, reset, branchOutc, instField[9:0], pcOut);
pgmCounter ProgramCounter (clk_d, reset, branch, romOut[9:0], pcOut);
// instruction ROM is declared using xilinx primitive
RAMB16_S18 rom ( .DI(),
.DIP(),
.ADDR(pcOut),
.EN(1'b1),
.WE(),
.SSR(1'b0),
.CLK(clk_d),
.DO(romOut),
.DOP());
// RAMB16_S18 rom ( .DI(),
// .DIP(),
// .ADDR(pcOut),
// .EN(1'b1),
// .WE(),
// .SSR(1'b0),
// .CLK(clk_d),
// .DO(romOut),
// .DOP());
 
// rom CodeMem (pcOut, romOut);
rom CodeMem (clk_d, pcOut, romOut);
 
// pipeline register
 
256,7 → 258,7
byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
inputRegister inputStorage (IN, instField2[6:0], inputReadOutData);
outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
/hdl/accumulator.v
12,7 → 12,7
reg [7:0] accOut;
 
always @ (accIn, accEn)
always @ (accEn)
begin
if (accEn)
begin
/hdl/alu.v
12,8 → 12,8
wire [8:0] addRes = operand1 + operand2;
wire [8:0] subRes = operand1 - operand2;
reg [8:0] aluOutput;
reg carryOutput;
reg [8:0] aluOut = 0;
reg carryOut = 0;
always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
begin
25,53 → 25,53
case (aluOpcode)
`AND_alu : begin
aluOutput = op1 & op2;
aluOut = op1 & op2;
end
`OR_alu : begin
aluOutput = op1 | op2;
aluOut = op1 | op2;
end
`XOR_alu : begin
aluOutput = op1^op2;
aluOut = op1^op2;
end
`GT_alu : begin
aluOutput = op1>op2 ? 1'b1 : 1'b0;
aluOut = op1>op2 ? 1'b1 : 1'b0;
end
`GE_alu : begin
aluOutput = op1>=op2 ? 1'b1 : 1'b0;
aluOut = op1>=op2 ? 1'b1 : 1'b0;
end
`EQ_alu : begin
aluOutput = op1==op2 ? 1'b1 : 1'b0;
aluOut = op1==op2 ? 1'b1 : 1'b0;
end
`LE_alu : begin
aluOutput = op1<=op2 ? 1'b1 : 1'b0;
aluOut = op1<=op2 ? 1'b1 : 1'b0;
end
`LT_alu : begin
aluOutput = op1<op2 ? 1'b1 : 1'b0;
aluOut = op1<op2 ? 1'b1 : 1'b0;
end
`ADD_alu : begin
aluOutput = addRes[7:0];
carryOutput = addRes[8];
aluOut = addRes[7:0];
carryOut = addRes[8];
end
`SUB_alu : begin
aluOutput = subRes[7:0];
carryOutput = subRes[8];
aluOut = subRes[7:0];
carryOut = subRes[8];
end
`LD_data : begin
aluOutput = op1;
aluOut = op2;
end
default : begin
aluOutput = 16'b0;
aluOut = 16'b0;
$write ("\nUnknown operation. \tmodule : ALU");
end
endcase
80,12 → 80,9
else
begin
aluOutput = aluOutput;
aluOut = aluOut;
end
end
assign aluOut = aluOutput;
assign carryOut = carryOutput;
endmodule
/hdl/pgmCounter.v
10,14 → 10,14
output [`instAddrLen-1:0] pcOut;
reg [`instAddrLen-1:0] pc = `instAddrLen'b0;
reg [`instAddrLen-1:0] pcOut = `instAddrLen'b0;
always @ (posedge clk or posedge reset)
always @ (posedge clk)
begin
if (reset)
begin
pc = `instAddrLen'b0;
pcOut = `instAddrLen'b0;
$write ("\nprogram counter module is reset. Starting at address 00h ");
end
26,18 → 26,15
if(branch)
begin
pc = pcIn;
pcOut = pcIn;
$write ("\nbranching at address %h", pcIn);
end
else
begin
pc = pc + 1'b1;
pcOut = pcOut + 1'b1;
end
end
end // end always
assign pcOut = pc;
 
 
endmodule
/hdl/op2Mux.v
11,10 → 11,10
output [7:0] op2MuxOut;
reg [7:0] op2MuxOut;
reg [7:0] op2MuxOut = 0;
always @ *
always @ (op2MuxSel)
begin
case (op2MuxSel)
37,7 → 37,7
default : begin
op2MuxOut = 8'bzzzzzzzz;
op2MuxOut = op2MuxOut;
end
endcase
/hdl/inputReg.v
4,41 → 4,18
 
 
 
module inputRegister (reset, inputs, inputRead, inputReadAddr, inputReadOut);
module inputRegister (inputs, inputReadAddr, inputReadOut);
 
input [`inputNumber-1:0] inputs;
input inputRead, reset;
input [`inputAddrLen-1:0] inputReadAddr;
output inputReadOut;
reg inputReadOut;
reg [`inputNumber-1:0] inputReg;
wire [`inputNumber-1:0] inputs;
always @ (reset or inputs or inputRead or inputReadAddr)
begin
if (reset)
begin
inputReadOut = 1'bz;
$write ("\nmodule inputRegister is reset ");
end
else
begin
inputReg = inputs;
if (inputRead)
begin
inputReadOut = inputReg [inputReadAddr];
$write ("\nreading input : module inputRegister ");
end
end
end
assign inputReadOut = inputs[inputReadAddr];
 
 
endmodule
/hdl/tb.v
42,7 → 42,7
reset = 1'b1;
initial
#500 reset = 0;
#50 reset = 0;
initial
begin

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