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URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

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Rev 6 → Rev 7

/trunk/hdl/instReg.v File deleted
/trunk/hdl/tcAccum.v
32,14 → 32,14
assign ACC_all[5] = tcAccumIn[(`tcAccLen*6)-1:(`tcAccLen*5)];
assign ACC_all[6] = tcAccumIn[(`tcAccLen*7)-1:(`tcAccLen*6)];
assign ACC_all[7] = tcAccumIn[(`tcAccLen*8)-1:(`tcAccLen*7)];
assign ACC_all[8] = tcAccumIn[(`tcAccLen*9)-1:(`tcAccLen*8)];
assign ACC_all[9] = tcAccumIn[(`tcAccLen*10)-1:(`tcAccLen*9)];
assign ACC_all[10] = tcAccumIn[(`tcAccLen*11)-1:(`tcAccLen*10)];
assign ACC_all[11] = tcAccumIn[(`tcAccLen*12)-1:(`tcAccLen*11)];
assign ACC_all[12] = tcAccumIn[(`tcAccLen*13)-1:(`tcAccLen*12)];
assign ACC_all[13] = tcAccumIn[(`tcAccLen*14)-1:(`tcAccLen*13)];
assign ACC_all[14] = tcAccumIn[(`tcAccLen*15)-1:(`tcAccLen*14)];
assign ACC_all[15] = tcAccumIn[(`tcAccLen*16)-1:(`tcAccLen*15)];
// assign ACC_all[8] = tcAccumIn[(`tcAccLen*9)-1:(`tcAccLen*8)];
// assign ACC_all[9] = tcAccumIn[(`tcAccLen*10)-1:(`tcAccLen*9)];
// assign ACC_all[10] = tcAccumIn[(`tcAccLen*11)-1:(`tcAccLen*10)];
// assign ACC_all[11] = tcAccumIn[(`tcAccLen*12)-1:(`tcAccLen*11)];
// assign ACC_all[12] = tcAccumIn[(`tcAccLen*13)-1:(`tcAccLen*12)];
// assign ACC_all[13] = tcAccumIn[(`tcAccLen*14)-1:(`tcAccLen*13)];
// assign ACC_all[14] = tcAccumIn[(`tcAccLen*15)-1:(`tcAccLen*14)];
// assign ACC_all[15] = tcAccumIn[(`tcAccLen*16)-1:(`tcAccLen*15)];
 
endmodule
/trunk/hdl/controlUnit.v
208,26 → 208,26
2'b11 : op2MuxSel = `op2MuxSelByteRam;
default: op2MuxSel = `op2MuxSelInput;
endcase
aluEn = 1;
aluEn = 1'b1;
aluOpcode = `LD_data;
bitRamEn = 1;
bitRamRw = 1;
byteRamEn = 1;
byteRamRw = 1;
inputRead = 1;
outputRw = 1;
bitRamEn = 1'b1;
bitRamRw = 1'b1;
byteRamEn = 1'b1;
byteRamRw = 1'b1;
inputRead = 1'b1;
outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end // end case Ld
238,29 → 238,29
`Ldi : begin
state = sAlu;
branch = 0;
branch = 1'b0;
accMuxSel = `accMuxSelImmData; // select imm data thr mux
accEn = 1; // acc enabled
op2MuxSel = 0;
aluOpcode = 0;
aluEn = 0;
bitRamEn = 0;
bitRamRw = 1;
byteRamEn = 0;
byteRamRw = 1;
inputRead = 0;
outputRw = 1;
accEn = 1'b1; // acc enabled
op2MuxSel = 1'b0;
aluOpcode = 1'b0;
aluEn = 1'b0;
bitRamEn = 1'b0;
bitRamRw = 1'b1;
byteRamEn = 1'b0;
byteRamRw = 1'b1;
inputRead = 1'b0;
outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end // end case Ldi
270,31 → 270,31
`ST : begin
state = sSt;
branch = 0;
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluEn = 0;
aluOpcode = 0;
inputRead = 0;
branch = 1'b0;
accMuxSel = 1'b0;
accEn = 1'b0;
op2MuxSel = 1'b0;
aluEn = 1'b0;
aluOpcode = 1'b0;
inputRead = 1'b0;
 
case (iomemCode)
2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
2'b01 : begin bitRamRw = 1'b0; byteRamRw = 1'b1; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end
2'b10 : begin bitRamRw = 1'b1; byteRamRw = 1'b0; outputRw = 1'b1; bitRamEn = 1'b1; byteRamEn = 1'b1; end
2'b11 : begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b0; end
default: begin bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1; end
endcase
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
 
end
304,20 → 304,20
`ADD : begin
state = sAlu;
aluOpcode = `ADD_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
326,20 → 326,20
`SUB : begin
state = sAlu;
aluOpcode = `SUB_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
351,20 → 351,20
`AND : begin
state = sAlu;
aluOpcode = `AND_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
374,20 → 374,20
`OR : begin
state = sAlu;
aluOpcode = `OR_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
397,20 → 397,20
`XOR : begin
state = sAlu;
aluOpcode = `XOR_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
420,20 → 420,20
`GrT : begin
state = sAlu;
aluOpcode = `GT_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
445,20 → 445,20
`GE : begin
state = sAlu;
aluOpcode = `GE_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
470,20 → 470,20
`EQ : begin
state = sAlu;
aluOpcode = `EQ_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
495,20 → 495,20
`LE : begin
state = sAlu;
aluOpcode = `LE_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
520,20 → 520,20
`LT : begin
state = sAlu;
aluOpcode = `LT_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b1;
branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timeAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
543,19 → 543,19
`PRE : begin
state = sTc;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b1; tcLoadEn = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
565,19 → 565,19
`ETY : begin
state = sTc;
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b1; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
588,19 → 588,19
`RST : begin
state = sTc;
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b1; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
611,20 → 611,20
`LdTC : begin
state = sTc;
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 1;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b1;
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
accMuxSel = `accMuxSelTcLoad; accEn = 1'b1; // loading TC status data
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
635,20 → 635,20
`LdACC : begin
state = sTc;
entypeEn = 0; tcAccRead = 1; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b1; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
accMuxSel = `accMuxSelTcAcc; accEn = 1'b1; // loading TC ACC data
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
660,20 → 660,20
`UARTrd : begin
state = sUart;
uartRead = 1; uartWrite = 0;
uartRead = 1'b1; uartWrite = 1'b0;
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
accMuxSel = `accMuxSelUartData; accEn = 1'b1; // loading UART data
aluEn = 0; aluOpcode = 0; branch = 0;op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
680,23 → 680,47
 
 
 
`ifdef UART_peripheral
`UARTstat : begin
state = sUart;
uartRead = 1'b0; uartWrite = 1'b0;
accMuxSel = `accMuxSelUartStat; accEn = 1'b1; // loading UART status
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
 
 
 
 
`ifdef UART_peripheral
`UARTwr : begin
state = sUart;
uartRead = 0; uartWrite = 1;
uartRead = 1'b0; uartWrite = 1'b1;
aluEn = 0; aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef SPI_peripheral
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
`endif
end
`endif
708,18 → 732,18
`SPIxFER : begin
state = sSpi;
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b1; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
731,18 → 755,18
`SPIstat : begin
state = sSpi;
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b1; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
754,18 → 778,18
`SPIwBUF : begin
state = sSpi;
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b1; spiBufShift = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
777,18 → 801,18
`SPIrBUF : begin
state = sSpi;
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b1; spiBufWrite = 1'b0; spiBufShift = 1'b0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
aluEn = 1'b0; aluOpcode = 1'b0; branch = 1'b0; accMuxSel = 1'b0; accEn = 1'b0; op2MuxSel = 1'b0;
bitRamEn = 1'b0; bitRamRw = 1'b1; byteRamEn = 1'b0; byteRamRw = 1'b1; inputRead = 1'b0; outputRw = 1'b1;
`ifdef timerAndCounter_peripheral
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
`endif
`ifdef UART_peripheral
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
`endif
end
807,26 → 831,26
sBr : begin
branch = 0;
branch = 1'b0;
state = s;
end // end case sBr
sLd : begin
aluEn = 0;
accEn = 1;
aluEn = 1'b0;
accEn = 1'b1;
accMuxSel = `accMuxSelAluOut;
state = s;
end // end case sLd
sSt : begin
bitRamRw = 1; byteRamRw = 1; outputRw = 1;
bitRamRw = 1'b1; byteRamRw = 1'b1; outputRw = 1'b1;
state = s;
end
sAlu : begin
aluEn = 0;
accEn = 1;
aluEn = 1'b0;
accEn = 1'b1;
accMuxSel = `accMuxSelAluOut;
state = s;
end
833,7 → 857,7
`ifdef timerAndCounter_peripheral
sTc : begin
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
entypeEn = 1'b0; tcAccRead = 1'b0; tcResetEn = 1'b0; tcPresetEn = 1'b0; tcLoadEn = 1'b0;
state = s;
end
`endif
840,7 → 864,7
 
`ifdef UART_peripheral
sUart : begin
uartRead = 0; uartWrite = 0;
uartRead = 1'b0; uartWrite = 1'b0;
state = s;
end
`endif
847,7 → 871,7
 
`ifdef SPI_peripheral
sSpi : begin
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
sconEn = 1'b0; spiStatRead = 1'b0; spiBufRead = 1'b0; spiBufWrite = 1'b0; spiBufShift = 1'b0;
state = s;
end
`endif
/trunk/hdl/top.v
58,6 → 58,8
`endif
`ifdef UART_peripheral
wire uartReadOutc, uartWriteOutc;
wire [7:0] uartDataOut;
wire rxEmpty, txFull;
`endif
`ifdef SPI_peripheral
wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
88,7 → 90,7
`ifdef timerAndCounter_peripheral
 
wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
wire [7:0] tcAccumOut;
wire [7:0] tcAccOut;
wire [7:0] tcLoadOut;
wire [`tcNumbers-1:0] enWires;
wire [`tcNumbers-1:0] resetWires;
118,7 → 120,7
//-------- Fetch Unit Module Instances
// all necessary
 
pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
pgmCounter ProgramCounter (clk, reset, branchOutc, instField[9:0], pcOut);
// instruction ROM is declared using xilinx primitive
132,7 → 134,7
.DO(romOut),
.DOP());
 
instReg IntructionRegister (romOut, instOpCode, instField);
// instReg IntructionRegister (romOut, instOpCode, instField);
 
 
// pipeline register
141,7 → 143,7
wire [`instFieldLen-1:0] instField1;
wire [`instFieldLen-1:0] instField2;
ppReg1 PipeLine_Reg1 (clk, instOpCode, instField, instOpCode1, instField1);
ppReg1 PipeLine_Reg1 (clk, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
215,7 → 217,7
, tcLoadOut, tcAccOut
`endif
`ifdef UART_peripheral
, uartDataOut
, uartDataOut, {rxEmpty, txFull}
`endif
`ifdef SPI_peripheral
, spiStatOut, spiBufOut
261,7 → 263,7
 
tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
/trunk/hdl/counter_all.v
3,118 → 3,118
`include "defines.v"
 
 
module counter (clk, reset, preset, type, DN, CU, CD, ACC);
 
input clk, reset;
input [`tcPresetLen-1:0] preset;
input [`tcTypeLen-1:0] type;
output DN, CU, CD;
output [`tcAccLen-1:0] ACC;
reg DN, CU, CD;
reg [`tcAccLen-1:0] ACC;
reg [`tcTypeLen-1:0] CounterType;
reg [`tcTypeLen-1:0] typeNext;
parameter UpCounter = `tcTypeLen'b01;
parameter DownCounter = `tcTypeLen'b10;
parameter defaultType = `tcTypeLen'b00;
always @ (type)
begin
case (type)
`counterType1 : begin
typeNext = UpCounter;
end
`counterType2 : begin
typeNext = DownCounter;
end
default : begin
$display ("counter is of undefined type.\n Valid types are Up counter & Down counter");
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
$display ("counter module is reset");
CounterType = defaultType;
end
else
begin
CounterType = typeNext;
end
end
always @ (posedge clk)
begin
case (CounterType)
UpCounter : begin
CD = 0; // CD id always 0 for this state
if (reset)
begin
ACC = `tcAccLen-1'b0; // starts at lowest value
CU = 0;
DN = 0;
end
else
begin
ACC = ACC + 1'b1;
CU = 1'b1;
if (ACC > preset)
begin
DN = 1'b1;
end
end
end
DownCounter : begin
CU = 0; // CU id always 0 for this state
if (reset)
begin
ACC = `tcAccLen-1'b1; // starts at highest value
CD = 0;
DN = 0;
end
else
begin
ACC = ACC - 1'b1;
CD = 1'b1;
if (ACC < preset)
begin
DN = 1'b1;
end
end
end
default : begin
$display (" error in counter type ");
end
endcase
end
 
 
endmodule
module counter (clk, reset, preset, type, DN, CU, CD, ACC);
 
input clk, reset;
input [`tcPresetLen-1:0] preset;
input [`tcTypeLen-1:0] type;
output DN, CU, CD;
output [`tcAccLen-1:0] ACC;
reg DN = 0, CU = 0, CD = 0;
reg [`tcAccLen-1:0] ACC = 0;
reg [`tcTypeLen-1:0] CounterType;
reg [`tcTypeLen-1:0] typeNext;
parameter UpCounter = `tcTypeLen'b01;
parameter DownCounter = `tcTypeLen'b10;
parameter defaultType = `tcTypeLen'b00;
always @ (type)
begin
case (type)
`counterType1 : begin
typeNext = UpCounter;
end
`counterType2 : begin
typeNext = DownCounter;
end
default : begin
$display ("counter is of undefined type.\n Valid types are Up counter & Down counter");
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
$display ("counter module is reset");
CounterType = defaultType;
end
else
begin
CounterType = typeNext;
end
end
always @ (posedge clk)
begin
case (CounterType)
UpCounter : begin
CD = 0; // CD id always 0 for this state
if (reset)
begin
ACC = `tcAccLen-1'b0; // starts at lowest value
CU = 0;
DN = 0;
end
else
begin
ACC = ACC + 1'b1;
CU = 1'b1;
if (ACC > preset)
begin
DN = 1'b1;
end
end
end
DownCounter : begin
CU = 0; // CU id always 0 for this state
if (reset)
begin
ACC = `tcAccLen-1'b1; // starts at highest value
CD = 0;
DN = 0;
end
else
begin
ACC = ACC - 1'b1;
CD = 1'b1;
if (ACC < preset)
begin
DN = 1'b1;
end
end
end
default : begin
$display (" error in counter type ");
end
endcase
end
 
 
endmodule
/trunk/hdl/defines.v
4,6 → 4,7
`define immDataLen 8
 
// program counter & instruction register
`define instAddrLen 10 // 10-bit address => 1024 inst in rom
`define instLen 15 // 15-bit fixed-length instructions
`define instOpCodeLen 5
`define instFieldLen 10
35,10 → 36,11
`define LdACC `instOpCodeLen'b10101
`define UARTrd `instOpCodeLen'b10110
`define UARTwr `instOpCodeLen'b10111
`define SPIxFER `instOpCodeLen'b11000
`define SPIstat `instOpCodeLen'b11001
`define SPIwBUF `instOpCodeLen'b11010
`define SPIrBUF `instOpCodeLen'b11011
`define UARTstat `instOpCodeLen'b11000
`define SPIxFER `instOpCodeLen'b11001
`define SPIstat `instOpCodeLen'b11010
`define SPIwBUF `instOpCodeLen'b11011
`define SPIrBUF `instOpCodeLen'b11100
 
// alu opcodes
`define aluOpcodeLen 4
79,9 → 81,10
`define accMuxSelAluOut `accMuxSelLen'b1
`define accMuxSelTcLoad `accMuxSelLen'b10
`define accMuxSelTcAcc `accMuxSelLen'b11
`define accMuxSelUart `accMuxSelLen'b100
`define accMuxSelSpiStat `accMuxSelLen'b101
`define accMuxSelSpiBuf `accMuxSelLen'b110
`define accMuxSelUartData `accMuxSelLen'b100
`define accMuxSelUartStat `accMuxSelLen'b101
`define accMuxSelSpiStat `accMuxSelLen'b110
`define accMuxSelSpiBuf `accMuxSelLen'b111
 
// operand2 multiplexer
`define op2MuxSelLen 4 // 2^4 = 16 selections available for op2
108,7 → 111,7
`define tcPresetLen 8 // 8-bit preset value
`define tcAddrLen 4
`define tcTypeLen 2 // max 4-types
`define tcNumbers 16 // total 16 modules (8-timers, 8-counters)
`define tcNumbers 8 // total 8 modules (4-timers, 4-counters)
 
`define timerType1 `tcTypeLen'b0
`define timerType2 `tcTypeLen'b1
/trunk/hdl/accMUX.v
8,7 → 8,7
, tcLoadIn, tcAccIn
`endif
`ifdef UART_peripheral
, uartDataIn
, uartDataIn, uartStatIn
`endif
`ifdef SPI_peripheral
, spiStatIn, spiBufIn
23,7 → 23,7
input [7:0] tcLoadIn, tcAccIn;
`endif
`ifdef UART_peripheral
input [7:0] uartDataIn;
input [7:0] uartDataIn, uartStatIn;
`endif
`ifdef SPI_peripheral
input [7:0] spiStatIn, spiBufIn;
58,9 → 58,13
`endif
`ifdef UART_peripheral
`accMuxSelUart : begin
`accMuxSelUartData : begin
accMuxOut = uartDataIn;
end
`accMuxSelUartStat : begin
accMuxOut = uartStatIn;
end
`endif
`ifdef SPI_peripheral
/trunk/hdl/alu.v
15,7 → 15,7
reg [8:0] aluOutput;
reg carryOutput;
always @ (op1 or op2 or aluOpcode)
always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
begin
 
/trunk/hdl/pgmCounter.v
6,11 → 6,11
module pgmCounter (clk, reset, branch, pcIn, pcOut);
 
input clk, reset, branch;
input [`instLen-1:0] pcIn;
input [`instAddrLen-1:0] pcIn;
output [`instLen-1:0] pcOut;
output [`instAddrLen-1:0] pcOut;
reg [`instLen-1:0] pc = `instLen'b0;
reg [`instAddrLen-1:0] pc = `instAddrLen'b0;
always @ (posedge clk or posedge reset)
begin
17,7 → 17,7
if (reset)
begin
pc = `instLen'b0;
pc = `instAddrLen'b0;
$write (" program counter module is reset. Starting at address 00h ");
end
/trunk/hdl/tcPreset.v
29,15 → 29,15
assign presetOut[(`tcPresetLen*5)-1:(`tcPresetLen*4)] = presets[4];
assign presetOut[(`tcPresetLen*6)-1:(`tcPresetLen*5)] = presets[5];
assign presetOut[(`tcPresetLen*7)-1:(`tcPresetLen*6)] = presets[6];
assign presetOut[(`tcPresetLen*8)-1:(`tcPresetLen*7)] = presets[7];
assign presetOut[(`tcPresetLen*9)-1:(`tcPresetLen*8)] = presets[8];
assign presetOut[(`tcPresetLen*10)-1:(`tcPresetLen*9)] = presets[9];
assign presetOut[(`tcPresetLen*11)-1:(`tcPresetLen*10)] = presets[10];
assign presetOut[(`tcPresetLen*12)-1:(`tcPresetLen*11)] = presets[11];
assign presetOut[(`tcPresetLen*13)-1:(`tcPresetLen*12)] = presets[12];
assign presetOut[(`tcPresetLen*14)-1:(`tcPresetLen*13)] = presets[13];
assign presetOut[(`tcPresetLen*15)-1:(`tcPresetLen*14)] = presets[14];
assign presetOut[(`tcPresetLen*16)-1:(`tcPresetLen*15)] = presets[15];
// assign presetOut[(`tcPresetLen*8)-1:(`tcPresetLen*7)] = presets[7];
// assign presetOut[(`tcPresetLen*9)-1:(`tcPresetLen*8)] = presets[8];
// assign presetOut[(`tcPresetLen*10)-1:(`tcPresetLen*9)] = presets[9];
// assign presetOut[(`tcPresetLen*11)-1:(`tcPresetLen*10)] = presets[10];
// assign presetOut[(`tcPresetLen*12)-1:(`tcPresetLen*11)] = presets[11];
// assign presetOut[(`tcPresetLen*13)-1:(`tcPresetLen*12)] = presets[12];
// assign presetOut[(`tcPresetLen*14)-1:(`tcPresetLen*13)] = presets[13];
// assign presetOut[(`tcPresetLen*15)-1:(`tcPresetLen*14)] = presets[14];
// assign presetOut[(`tcPresetLen*16)-1:(`tcPresetLen*15)] = presets[15];
 
endmodule
/trunk/hdl/timer_all.v
1,197 → 1,189
 
 
 
 
 
 
 
 
`include "timescale.v"
`include "defines.v"
 
 
 
module timer (clk, en, reset, type, preset, DN, TT, ACC);
 
input clk, en, reset;
input [`tcTypeLen-1:0] type;
input [`tcPresetLen-1:0] preset;
output DN, TT;
output [`tcAccLen-1:0] ACC;
reg DN, TT;
reg [`tcAccLen-1:0] ACC;
reg [`tcTypeLen-1:0] TimerType;
reg [`tcTypeLen-1:0] typeNext;
 
parameter OnDelayTimer = `tcTypeLen'b0;
parameter OffDelayTimer = `tcTypeLen'b1;
parameter RetOnDelayTimer = `tcTypeLen'b10;
parameter defaultType = `tcTypeLen'b11;
always @ (type)
begin
case (type)
`timerType1 : begin
typeNext = OnDelayTimer;
end
`timerType2 : begin
typeNext = OffDelayTimer;
end
`timerType3 : begin
typeNext = RetOnDelayTimer;
end
default : begin
 
$display(" Timer is defined for unknown type.\n Valid types: On-delay, Off-delay, retentive-on-delay");
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
$write (" timer module is reset ");
TimerType = defaultType;
end
else
begin
TimerType = typeNext;
end
end
always @ (posedge clk)
begin
 
case (TimerType)
OnDelayTimer : begin
if (reset)
begin
ACC = `tcAccLen'b0;
DN = 1'b0;
TT = 1'b0;
end
else
begin
if (en)
begin
if (ACC < preset)
begin
ACC = ACC + 1'b1;
DN = 1'b0;
TT = 1'b1;
end
else if (ACC >= preset)
begin
ACC = ACC;
 
DN = 1'b1;
TT = 1'b0;
end
end
else
begin
ACC = `tcAccLen'b0; // if not enabled
DN = 1'b0;
TT = 1'b0;
end
end
end // end this case
OffDelayTimer : begin // not correct implementation!
if (reset)
begin
ACC = `tcAccLen'b0;
DN = 1'b0;
TT = 1'b0;
end
else
begin
if (!en)
begin
if (ACC < preset)
begin
ACC = ACC + 1'b1;
DN = 1'b0;
TT = 1'b1;
end
else if (ACC >= preset)
begin
ACC = ACC;
DN = 1'b1;
TT = 1'b0;
end
end
else
begin
ACC = `tcAccLen'b0; // if not enabled
DN = 1'b0;
TT = 1'b0;
end
end
end // end this case
RetOnDelayTimer : begin
 
if (reset)
begin
ACC = `tcAccLen'b0;
DN = 1'b0;
TT = 1'b0;
end
else
begin
if (en)
begin
if (ACC < preset)
begin
ACC = ACC + 1'b1;
DN = 1'b0;
TT = 1'b1;
end
else if (ACC >= preset)
begin
ACC = ACC;
DN = 1'b1;
 
 
 
 
TT = 1'b0;
end
end
else
begin
ACC = ACC; // retain ACC
DN = 1'b0;
TT = 1'b0;
end
end
end // end this case
default : begin
$display(" Error in timer type ");
end
endcase
end
 
endmodule
 
module timer (clk, en, reset, type, preset, DN, TT, ACC);
 
input clk, en, reset;
input [`tcTypeLen-1:0] type;
input [`tcPresetLen-1:0] preset;
output DN, TT;
output [`tcAccLen-1:0] ACC;
reg DN = 0, TT = 0;
reg [`tcAccLen-1:0] ACC = 0;
reg [`tcTypeLen-1:0] TimerType;
reg [`tcTypeLen-1:0] typeNext;
 
parameter OnDelayTimer = `tcTypeLen'b0;
parameter OffDelayTimer = `tcTypeLen'b1;
parameter RetOnDelayTimer = `tcTypeLen'b10;
parameter defaultType = `tcTypeLen'b11;
always @ (type)
begin
case (type)
`timerType1 : begin
typeNext = OnDelayTimer;
end
`timerType2 : begin
typeNext = OffDelayTimer;
end
`timerType3 : begin
typeNext = RetOnDelayTimer;
end
default : begin
 
$display(" Timer is defined for unknown type.\n Valid types: On-delay, Off-delay, retentive-on-delay");
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
$write (" timer module is reset ");
TimerType = defaultType;
end
else
begin
TimerType = typeNext;
end
end
always @ (posedge clk)
begin
 
case (TimerType)
OnDelayTimer : begin
if (reset)
begin
ACC = `tcAccLen'b0;
DN = 1'b0;
TT = 1'b0;
end
else
begin
if (en)
begin
if (ACC < preset)
begin
ACC = ACC + 1'b1;
DN = 1'b0;
TT = 1'b1;
end
else if (ACC >= preset)
begin
ACC = ACC;
 
DN = 1'b1;
TT = 1'b0;
end
end
else
begin
ACC = `tcAccLen'b0; // if not enabled
DN = 1'b0;
TT = 1'b0;
end
end
end // end this case
OffDelayTimer : begin // not correct implementation!
if (reset)
begin
ACC = `tcAccLen'b0;
DN = 1'b0;
TT = 1'b0;
end
else
begin
if (!en)
begin
if (ACC < preset)
begin
ACC = ACC + 1'b1;
DN = 1'b0;
TT = 1'b1;
end
else if (ACC >= preset)
begin
ACC = ACC;
DN = 1'b1;
TT = 1'b0;
end
end
else
begin
ACC = `tcAccLen'b0; // if not enabled
DN = 1'b0;
TT = 1'b0;
end
end
end // end this case
RetOnDelayTimer : begin
 
if (reset)
begin
ACC = `tcAccLen'b0;
DN = 1'b0;
TT = 1'b0;
end
else
begin
if (en)
begin
if (ACC < preset)
begin
ACC = ACC + 1'b1;
DN = 1'b0;
TT = 1'b1;
end
else if (ACC >= preset)
begin
ACC = ACC;
DN = 1'b1;
 
 
 
 
TT = 1'b0;
end
end
else
begin
ACC = ACC; // retain ACC
DN = 1'b0;
TT = 1'b0;
end
end
end // end this case
default : begin
if (!reset)
$display(" Error in timer type ");
end
endcase
end
 
endmodule

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