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URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

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  • This comparison shows the changes necessary to convert path 
    /instruction_list_pipelined_processor_with_peripherals
    from Rev 7 to Rev 8
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  •

Rev 7 → Rev 8

/trunk/hdl/ramBit.v
20,7 → 20,7
if (reset)
begin
bitRamOut = 1'b0;
$write (" module bitRam is reset ");
$write ("\nmodule bitRam is reset ");
end
else
31,13 → 31,13
if (bitRamRw) // read operation
begin
bitRamOut = bitRam[bitRamAddr];
$write (" reading bit-RAM : module bitRAM ");
// $write ("\nreading bit-RAM : module bitRAM ");
end
else // write operation
begin
bitRam[bitRamAddr] = bitRamIn;
$write (" writing to bit-RAM : module bitRam ");
// $write ("\nwriting to bit-RAM : module bitRam ");
end
end
/trunk/hdl/tcAccum.v
20,7 → 20,7
if (tcAccumRead)
begin
tcAccumOut = ACC_all[tcAddr];
$write (" reading t/c accumulated value : module tcAccum ");
$write ("\nreading t/c accumulated value : module tcAccum ");
end
end
/trunk/hdl/controlUnit.v
820,8 → 820,8
 
default : begin
$write (" unknown/unused instruction op-code encountered by control unit ");
$stop;
$write ("\nunknown/unused instruction op-code encountered by control unit ");
// $stop;
end
endcase // end case (instOpCode)
/trunk/hdl/top.v
30,7 → 30,7
 
// wires (interconnects) of execution unit
 
wire [`instLen-1:0] pcOut;
wire [`instAddrLen-1:0] pcOut;
wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
wire [`instOpCodeLen-1:0] instOpCode;
wire [`instFieldLen-1:0] instField;
100,27 → 100,36
 
`endif
 
// wires (interconnects) of UART
`ifdef SPI_peripheral
 
`ifdef UART_peripheral
wire [7:0] spiStatOut, spiBufOut;
`endif
 
 
wire clk_d, clk_t;
reg [10:0] cnt = 0;
`endif
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
cnt =0;
end
else
begin
cnt = cnt + 1'b1;
end
end
// wires (interconnects) of SPI
assign clk_d = cnt[0];
assign clk_t = cnt[10];
 
`ifdef SPI_peripheral
`endif
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
pgmCounter ProgramCounter (clk, reset, branchOutc, instField[9:0], pcOut);
pgmCounter ProgramCounter (clk_d, reset, branchOutc, instField[9:0], pcOut);
// instruction ROM is declared using xilinx primitive
130,13 → 139,12
.EN(1'b1),
.WE(),
.SSR(1'b0),
.CLK(clk),
.CLK(clk_d),
.DO(romOut),
.DOP());
 
// instReg IntructionRegister (romOut, instOpCode, instField);
// rom CodeMem (pcOut, romOut);
 
 
// pipeline register
 
wire [`instOpCodeLen-1:0] instOpCode1;
143,7 → 151,7
wire [`instFieldLen-1:0] instField1;
wire [`instFieldLen-1:0] instField2;
ppReg1 PipeLine_Reg1 (clk, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
271,13 → 279,13
tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
timer timer2 (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
timer timer3 (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
/trunk/hdl/ramByte.v
20,7 → 20,7
if (reset)
begin
byteRamOut = `byteRamLen'b0;
$write (" module byteRam is reset ");
$write ("\nmodule byteRam is reset ");
end
else
32,7 → 32,7
if (byteRamRw) // read operation
begin
byteRamOut = byteRam[byteRamAddr];
$write (" reading byte RAM : module byteRam ");
// $write ("\nreading byte RAM : module byteRam ");
end
39,7 → 39,7
else // write operation
begin
byteRam[byteRamAddr] = byteRamIn;
$write (" writing to byte RAM : module byteRam ");
// $write ("\nwriting to byte RAM : module byteRam ");
end
end
/trunk/hdl/counter_all.v
39,7 → 39,7
end
default : begin
$display ("counter is of undefined type.\n Valid types are Up counter & Down counter");
$display ("\ncounter is of undefined type.\n Valid types are Up counter & Down counter");
end
endcase
end
110,7 → 110,7
default : begin
$display (" error in counter type ");
$display ("\nerror in counter type ");
end
endcase
/trunk/hdl/defines.v
1,6 → 1,6
// 16-bit process controller defines
// 16-bit process controller defines
 
// 8-bit Pipelined Processor defines
 
`define immDataLen 8
 
// program counter & instruction register
/trunk/hdl/spi_top.v
19,7 → 19,7
wire [7:0] buffer_out8;
spiStatReg STATUS_REG (statREAD, statOUT, BF);
spiStatReg STATUS_REG (BF, statREAD, statOUT);
 
 
spiConReg CONTROL_REG (sconEN, sconIN, sconOUT);
/trunk/hdl/accumulator.v
17,7 → 17,7
if (accEn)
begin
accOut = accIn;
$write (" %b data written to accumulator : module accumulator ", accIn);
$write ("\n%b data written to accumulator : module accumulator ", accIn);
end
else
begin
/trunk/hdl/alu.v
72,7 → 72,7
default : begin
aluOutput = 16'b0;
$write ("Unknown operation. \nmodule : ALU");
$write ("\nUnknown operation. \tmodule : ALU");
end
endcase
/trunk/hdl/pgmCounter.v
18,7 → 18,7
if (reset)
begin
pc = `instAddrLen'b0;
$write (" program counter module is reset. Starting at address 00h ");
$write ("\nprogram counter module is reset. Starting at address 00h ");
end
else
27,7 → 27,7
if(branch)
begin
pc = pcIn;
$write (" branching at address %h", pcIn);
$write ("\nbranching at address %h", pcIn);
end
else
begin
/trunk/hdl/inputReg.v
22,7 → 22,7
if (reset)
begin
inputReadOut = 1'bz;
$write (" module inputRegister is reset ");
$write ("\nmodule inputRegister is reset ");
end
else
33,7 → 33,7
if (inputRead)
begin
inputReadOut = inputReg [inputReadAddr];
$write (" reading input : module inputRegister ");
$write ("\nreading input : module inputRegister ");
end
end
/trunk/hdl/outputReg.v
13,8 → 13,8
output [`outputNumber-1:0] outputs;
reg outputReadOut;
reg [`outputNumber-1:0] outputs;
reg [`outputNumber-1 :0] outputReg;
reg [`outputNumber-1:0] outputs = 0;
reg [`outputNumber-1 :0] outputReg = 0;
24,7 → 24,7
if (reset)
begin
outputReadOut = 1'bz;
$write (" module outputRegister is reset ");
$write ("\nmodule outputRegister is reset ");
end
else
35,12 → 35,12
if (outputRw) // read output status
begin
outputReadOut = outputReg[outputRwAddr];
$write (" reading output register : module outputRegister ");
// $write ("\nreading output register : module outputRegister ");
end
else // write operation
begin
outputReg[outputRwAddr] = outputWriteIn;
$write (" writing to the output register : module outputRegister ");
// $write ("\nwriting to the output register : module outputRegister ");
end
end
/trunk/hdl/tb.v
0,0 → 1,55
 
`include "timescale.v"
`include "defines.v"
 
 
module tb;
 
reg clk, reset;
reg [`inputNumber-1:0] IN;
wire [`outputNumber-1:0] OUT;
`ifdef UART_peripheral
reg rx;
wire tx;
`endif
`ifdef SPI_peripheral
reg MISO;
wire MOSI, SCK;
`endif
top DUT(clk, reset, IN, OUT
 
`ifdef UART_peripheral
, rx, tx
`endif
`ifdef SPI_peripheral
, MISO, MOSI, SCK
`endif
);
initial
clk = 0;
always
#10 clk = ~clk;
initial
reset = 1'b1;
initial
#500 reset = 0;
initial
begin
IN = 0;
rx = 0;
MISO = 0;
end
 
endmodule
/trunk/hdl/timer_all.v
43,7 → 43,7
default : begin
 
$display(" Timer is defined for unknown type.\n Valid types: On-delay, Off-delay, retentive-on-delay");
$display("\nTimer is defined for unknown type.\n Valid types: On-delay, Off-delay, retentive-on-delay");
end
endcase
54,7 → 54,7
begin
if (reset)
begin
$write (" timer module is reset ");
$write ("\ntimer module is reset ");
TimerType = defaultType;
end
else
178,7 → 178,7
default : begin
if (!reset)
$display(" Error in timer type ");
$display("\nError in timer type ");
end
endcase

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