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    /integer_square_root/tags/v2.0/src
    from Rev 7 to Rev 2
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Rev 7 → Rev 2

/ISR.sv
154,3 → 154,9
 
 
endmodule
 
 
 
 
 
 
/test_ISR.sv
1,9 → 1,10
`define HALF_CYCLE 1000
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yihua Liu
//
// Create Date: 2022/10/14 01:01:28
// Create Date: 2022/06/08 16:51:12
// Design Name:
// Module Name: testbench
// Project Name: lab_3_b
15,7 → 16,6
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - Update Testbench
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
23,116 → 23,157
 
module testbench();
 
logic [63:0] test_input;
logic clock, reset, quit;
logic [63:0] value;
logic clock, reset;
 
logic [31:0] result;
logic done;
logic [31:0] cres;
 
integer i;
wire correct = (cres===result)|~done|reset;
integer value_test, j;
time start_time = $time, finish_time;
 
ISR UUT(
task ISR_test;
input [63:0] value;
output [31:0] cres;
cres = 0;
for (integer i = 31; i >= 0; i--) begin
cres[i] = 1;
if (cres * cres > value)
cres[i] = 0;
end
endtask
 
ISR isr(
.reset(reset),
.value(test_input),
.value(value),
.clock(clock),
.result(result),
.done(done)
);
 
task compare_correct_result;
input [63:0] value;
input [31:0] result;
 
logic [31:0] guess;
logic [63:0] multi;
begin
// First, calculate the correct result
guess = 32'h8000_0000;
for (i = 0; i <= 31; i = i + 1) begin
guess[31 - i] = 1'b1;
multi = {32'b0, guess};
if ((multi * multi) > value) begin
guess[31 - i] = 1'b0;
end
end
// Then, compare the result with the correct one
if (result == guess) begin
end
else begin
$display("@@@Failed");
$display("Incorrect at time %4.0f",$time);
$display("corrent_result = %h result = %h", guess, result);
$finish;
end
always @(posedge clock)
#2 if(!correct) begin
$display("Incorrect at time %4.0f",$time);
$display("cres = %h result = %h",cres,result);
$display("@@@Failed");
$finish;
end
endtask
 
 
always begin
#250;
clock = ~clock;
#`HALF_CYCLE;
clock=~clock;
end
 
// Some users have had problems just using "@(posedge done)" because their
// "done" signals glitch (even though they are the output of a register). This
// prevents that by making sure "done" is high at the clock edge.
task wait_until_done;
forever begin : wait_loop
@(posedge done);
@(negedge clock);
if (done) disable wait_until_done;
if(done) begin
finish_time = $time;
$display("Done one calculation of ISR");
// Calculate the total number of cycles you need to do one calculation of ISR
// Note that in this way the additional cycles added during simulation will be counted
// So the displayed value may be 1 to 3 cycles more than 600 cycles
$display("Number of cycles needed: %d", (finish_time - start_time) / (2 * `HALF_CYCLE));
start_time = finish_time;
disable wait_until_done;
end
end
endtask
 
 
initial begin
$dumpvars;
$monitor("Time:%4.0f done:%b input:%h result:%h ",$time, done, test_input, result);
reset = 0;
$monitor("Time:%4.0f done:%b cres:%h result:%h reset:%h",$time,done,cres,result,reset);
// Test 1
value = 0; // square number
reset = 1;
clock = 0;
 
// First some special cases
test_input = 64'h0000_0000_0000_03E9;
ISR_test(value, cres);
#2000;
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
// Test 2
reset = 1;
value = 4; // square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
// Test 3
reset = 1;
value = 121; // square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
$display("Calculate done!");
compare_correct_result(test_input, result);
@(negedge clock);
// Test 4
reset = 1;
value = 1000000; // square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
// Test 5
reset = 1;
test_input = 64'hFFFF_FFFF_FFFF_FFFF;
value = 130; // non square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
compare_correct_result(test_input, result);
// Test 6
@(negedge clock);
reset = 1;
test_input = 64'h0000_0000_0000_0000;
value = 2; // non square number (value to be discarded)
ISR_test(value, cres);
@(negedge clock);
reset = 0;
@(negedge clock);
@(negedge clock);
@(negedge clock);
reset = 1; // reset is asserted part way through a computation
value = 3; // non square number (new value to be latched into)
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
compare_correct_result(test_input, result);
// Then some random tests
@(negedge clock);
@(negedge clock);
// Test 7
reset = 1;
value = 64'h7FFF_FFFF_FFFF_FFFF;
ISR_test(value, cres);
@(negedge clock);
quit = 0;
quit <= #100000 1;
while (~quit) begin
reset = 0;
wait_until_done();
@(negedge clock);
value_test = 64'hFFFF_FFFF_FFFF_FFFF;
// Short loops
for (j = 0; j < 100; j++) begin
reset = 1;
test_input = {$random, $random};
value = value_test;
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
compare_correct_result(test_input, result);
value_test = value_test - 64'h0000_0000_7FFF_FFFF;
end
@(negedge clock);
reset = 1;
@(negedge clock);
$display("@@@Passed");
// Random testing
for (j = 0; j < 1000; j++) begin
reset = 1;
value = {$random, $random};
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
end
$display("@@@Passed");
$finish;
end
 

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