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Rev 3 → Rev 5

/v1.1/src/ISR.sv
0,0 → 1,87
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yihua Liu
//
// Create Date: 2022/06/08 16:50:36
// Design Name:
// Module Name: ISR
// Project Name: lab_3_b
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
module ISR(
input reset,
input [63:0] value,
input clock,
output logic [31:0] result,
output logic done
);
logic [63:0] new_value, proposed_solution_square;
logic [31:0] proposed_solution;
logic [4:0] i;
logic start, it_done, flush;
logic reset_sync;
mult Multiplier (
.clock(clock),
.reset(reset),
.mcand({32'h00000000, proposed_solution}),
.mplier({32'h00000000, proposed_solution}),
.start(start),
.product(proposed_solution_square),
.done(it_done)
);
always_comb begin
// if (reset_async) begin
// done = 0;
// result = 0;
// end
// else begin
// Reduction operator
// see http://www.asic-world.com/verilog/operators2.html
// done = ~|i & it_done & ~flush;
// result[i] = (proposed_solution_square <= new_value) & it_done;
done = ~|i & it_done & ~flush & ~reset_sync;
result[i] = (proposed_solution_square <= new_value) & it_done & ~reset_sync;
// end
end
 
always_ff @(posedge clock or posedge reset) begin
if (reset) begin
// done <= 0;
// result <= 0;
reset_sync <= 1;
start <= 0;
flush <= 0;
i <= 5'b11111;
proposed_solution <= 32'h80000000;
new_value <= value;
end
else begin
reset_sync <= 0;
start <= !it_done || !flush;
flush <= it_done;
// if (!it_done && flush) begin
// flush <= 0;
// end
if (i && it_done && !flush) begin
// flush <= 1;
i <= i - 1;
proposed_solution[i-1] <= 1;
proposed_solution[i] <= result[i];
end
end
end
endmodule
/v1.1/src/mult_stage.sv
0,0 → 1,68
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yihua Liu
//
// Create Date: 2022/06/06 12:58:15
// Design Name:
// Module Name: mult_stage
// Project Name: lab_3_a
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
// This is one stage of an 8 stage (9 depending on how you look at it)
// pipelined multiplier that multiplies 2 64-bit integers and returns
// the low 64 bits of the result. This is not an ideal multiplier but
// is sufficient to allow a faster clock period than straight *
module mult_stage(
input clock, reset, start,
input [63:0] product_in, mplier_in, mcand_in,
 
output logic done,
output logic [63:0] product_out, mplier_out, mcand_out
);
 
// This parameter is used to change the number of stages.
// For example, if N_STAGE = 8, we are using an 8-stage pipelined multiplier.
parameter N_STAGE = 8;
logic [63:0] prod_in_reg, partial_prod_reg;
logic [63:0] partial_product, next_mplier, next_mcand;
 
assign product_out = prod_in_reg + partial_prod_reg;
 
assign partial_product = mplier_in[64/N_STAGE-1:0] * mcand_in;
 
// assign next_mplier = {{(64/N_STAGE){1'b0}},mplier_in[63:64/N_STAGE]};
// assign next_mcand = {mcand_in[64-64/N_STAGE-1:0],{(64/N_STAGE){1'b0}}};
assign next_mplier = mplier_in >> 64/N_STAGE;
assign next_mcand = mcand_in << 64/N_STAGE;
 
//synopsys sync_set_reset "reset"
always_ff @(posedge clock) begin
prod_in_reg <= #1 product_in;
partial_prod_reg <= #1 partial_product;
mplier_out <= #1 next_mplier;
mcand_out <= #1 next_mcand;
end
 
// synopsys sync_set_reset "reset"
always_ff @(posedge clock) begin
if(reset)
done <= #1 1'b0;
else
done <= #1 start;
end
 
endmodule
 
/v1.1/src/pipe_mult.sv
0,0 → 1,57
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yihua Liu
//
// Create Date: 2022/06/06 13:54:21
// Design Name:
// Module Name: mult
// Project Name: lab_3_a
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
// This is an 8 stage (9 depending on how you look at it) pipelined
// multiplier that multiplies 2 64-bit integers and returns the low 64 bits
// of the result. This is not an ideal multiplier but is sufficient to
// allow a faster clock period than straight *
// This module instantiates 8 pipeline stages as an array of submodules.
module mult(
input clock, reset,
input [63:0] mcand, mplier,
input start,
output [63:0] product,
output done
);
 
// This parameter is used to change the number of stages.
// For example, if N_STAGE = 8, we are using an 8-stage pipelined multiplier.
parameter N_STAGE = 8;
logic [63:0] mcand_out, mplier_out;
logic [(N_STAGE-1)*64-1:0] internal_products, internal_mcands, internal_mpliers;
logic [N_STAGE-2:0] internal_dones;
mult_stage #(.N_STAGE(N_STAGE)) mstage [N_STAGE-1:0] (
.clock(clock),
.reset(reset),
.product_in({internal_products,64'h0}),
.mplier_in({internal_mpliers,mplier}),
.mcand_in({internal_mcands,mcand}),
.start({internal_dones,start}),
.product_out({product,internal_products}),
.mplier_out({mplier_out,internal_mpliers}),
.mcand_out({mcand_out,internal_mcands}),
.done({done,internal_dones})
);
 
endmodule
/v1.1/src/test_ISR.sv
0,0 → 1,180
`define HALF_CYCLE 1000
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yihua Liu
//
// Create Date: 2022/06/08 16:51:12
// Design Name:
// Module Name: testbench
// Project Name: lab_3_b
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
module testbench();
 
logic [63:0] value;
logic clock, reset;
 
logic [31:0] result;
logic done;
logic [31:0] cres;
 
wire correct = (cres===result)|~done|reset;
integer value_test, j;
time start_time = $time, finish_time;
 
task ISR_test;
input [63:0] value;
output [31:0] cres;
cres = 0;
for (integer i = 31; i >= 0; i--) begin
cres[i] = 1;
if (cres * cres > value)
cres[i] = 0;
end
endtask
 
ISR isr(
.reset(reset),
.value(value),
.clock(clock),
.result(result),
.done(done)
);
 
always @(posedge clock)
#2 if(!correct) begin
$display("Incorrect at time %4.0f",$time);
$display("cres = %h result = %h",cres,result);
$display("@@@Failed");
$finish;
end
 
always begin
#`HALF_CYCLE;
clock=~clock;
end
 
task wait_until_done;
forever begin : wait_loop
@(posedge done);
@(negedge clock);
if(done) begin
finish_time = $time;
$display("Done one calculation of ISR");
// Calculate the total number of cycles you need to do one calculation of ISR
// Note that in this way the additional cycles added during simulation will be counted
// So the displayed value may be 1 to 3 cycles more than 600 cycles
$display("Number of cycles needed: %d", (finish_time - start_time) / (2 * `HALF_CYCLE));
start_time = finish_time;
disable wait_until_done;
end
end
endtask
 
initial begin
$monitor("Time:%4.0f done:%b cres:%h result:%h reset:%h",$time,done,cres,result,reset);
// Test 1
value = 0; // square number
reset = 1;
clock = 0;
ISR_test(value, cres);
#2000;
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
// Test 2
reset = 1;
value = 4; // square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
// Test 3
reset = 1;
value = 121; // square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
// Test 4
reset = 1;
value = 1000000; // square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
// Test 5
reset = 1;
value = 130; // non square number
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
// Test 6
@(negedge clock);
reset = 1;
value = 2; // non square number (value to be discarded)
ISR_test(value, cres);
@(negedge clock);
reset = 0;
@(negedge clock);
@(negedge clock);
@(negedge clock);
reset = 1; // reset is asserted part way through a computation
value = 3; // non square number (new value to be latched into)
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
@(negedge clock);
// Test 7
reset = 1;
value = 64'h7FFF_FFFF_FFFF_FFFF;
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
@(negedge clock);
value_test = 64'hFFFF_FFFF_FFFF_FFFF;
// Short loops
for (j = 0; j < 100; j++) begin
reset = 1;
value = value_test;
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
value_test = value_test - 64'h0000_0000_7FFF_FFFF;
end
// Random testing
for (j = 0; j < 1000; j++) begin
reset = 1;
value = {$random, $random};
ISR_test(value, cres);
@(negedge clock);
reset = 0;
wait_until_done();
end
$display("@@@Passed");
$finish;
end
 
endmodule
/v1.1/README.md
0,0 → 1,48
# Integer Square Root
 
## Algorithm
 
```
procedure ISR(value)
for i<-31 to 0 do
proposed_solution[i]<-1
if proposed_solution^2 > value then
proposed_solution[i]<-0
end if
end for
end procedure
```
 
## Specification
 
- If reset is asserted during a rising clock edge (synchronous reset), the value signal is to be stored.
- If reset is asserted part way through a computation, the result of that computation is discarded and a new value is latched into the module.
- When the module has finished computing the answer, the output is placed on the result line and done line is raised on the same cycle.
- It must not take more than 600 clock cycles to compute a result (from the last
clock that reset is asserted to the first clock that done is asserted.)
 
## ISR State Machine
 
Computing: $\sqrt{\mathtt{value}}$
 
- On a reset
- guess initialized to `32'h8000_0000`
- `value` is clocked into a register
- guess gets the next bit set each time we cycle through the FSM again
 
- Square `guess` (multiply it with itself)
 
- Wait until the multiplier raises its done
 
- if `guess` <= `value`
 
- Keep the current bit
- else
 
- Clear the current bit
 
- Move to the next bit
 
- After the last bit, raise `done`

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