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URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /ion/trunk/sim
    from Rev 118 to Rev 127
    ↔ Reverse comparison
  •

Rev 118 → Rev 127

/mips_tb2.do
8,11 → 8,15
vcom -reportprogress 300 -work work ../vhdl/mips_alu.vhdl
vcom -reportprogress 300 -work work ../vhdl/mips_mult.vhdl
vcom -reportprogress 300 -work work ../vhdl/mips_cpu.vhdl
vcom -reportprogress 300 -work work ../vhdl/sdram_controller.vhdl
vcom -reportprogress 300 -work work ../vhdl/mips_cache_stub.vhdl
vcom -reportprogress 300 -work work ../vhdl/mips_cache.vhdl
#vcom -reportprogress 300 -work work ../vhdl/mips_memory_interface.vhdl
 
vcom -reportprogress 300 -work work ../vhdl/tb/txt_util.vhdl
vcom -reportprogress 300 -work work ../vhdl/tb/mips_tb_pkg.vhdl
vlog -reportprogress 300 -work work ../vhdl/tb/models/mt48lc4m16a2.v
 
vcom -reportprogress 300 -work work ../vhdl/tb/mips_tb2.vhdl
 
vsim -t ps work.mips_tb2(testbench)
/mips_tb2_wave.do
22,33 → 22,42
add wave -noupdate -color {Light Blue} -format Literal -radix hexadecimal /mips_tb2/log_info.pending_data_wr
add wave -noupdate -color {Light Blue} -format Literal -radix binary /mips_tb2/log_info.pending_data_wr_we
add wave -noupdate -divider Cache
add wave -noupdate -format Literal -radix hexadecimal /mips_tb2/cache/code_line_table
add wave -noupdate -format Literal -radix hexadecimal /mips_tb2/cache/code_line_addr
add wave -noupdate -format Literal /mips_tb2/cache/code_cache_tag
add wave -noupdate -format Literal /mips_tb2/cache/code_tag
add wave -noupdate -format Logic /mips_tb2/cache/cache_enable
add wave -noupdate -color Pink -format Literal /mips_tb2/cache/ps
add wave -noupdate -format Literal /mips_tb2/cache/code_refill_ctr
add wave -noupdate -group SDRAM
add wave -noupdate -group SDRAM -color {Cornflower Blue} -format Literal -radix hexadecimal /mips_tb2/sram_data_rd
add wave -noupdate -group SDRAM -color {Cadet Blue} -format Literal -radix hexadecimal /mips_tb2/sram_data_wr
add wave -noupdate -group SDRAM -format Literal -radix hexadecimal -expand /mips_tb2/sram_chip_addr
add wave -noupdate -group SDRAM -color {Slate Blue} -format Literal -radix hexadecimal /mips_tb2/sram_address
add wave -noupdate -group SDRAM -color Violet -format Literal /mips_tb2/sram_byte_we_n
add wave -noupdate -group SDRAM -color {Dark Orchid} -format Logic /mips_tb2/sram_oe_n
add wave -noupdate -format Literal -radix hexadecimal /mips_tb2/cache/data_wr_reg
add wave -noupdate -format Literal -radix hexadecimal /mips_tb2/cache/data_wr_addr_reg
add wave -noupdate -group SRAM
add wave -noupdate -group SRAM -color {Cornflower Blue} -format Literal -radix hexadecimal /mips_tb2/sram_data_rd
add wave -noupdate -group SRAM -color {Cadet Blue} -format Literal -radix hexadecimal /mips_tb2/sram_data_wr
add wave -noupdate -group SRAM -format Literal -radix hexadecimal /mips_tb2/sram_chip_addr
add wave -noupdate -group SRAM -color {Slate Blue} -format Literal -radix hexadecimal /mips_tb2/sram_address
add wave -noupdate -group SRAM -color Violet -format Literal -expand /mips_tb2/sram_byte_we_n
add wave -noupdate -group SRAM -color {Dark Orchid} -format Logic /mips_tb2/sram_oe_n
add wave -noupdate -group I-Cache
add wave -noupdate -group I-Cache -format Literal /mips_tb2/cache/code_refill_ctr
add wave -noupdate -group I-Cache -format Logic /mips_tb2/cache/code_wait
add wave -noupdate -group I-Cache -color Orange -format Logic /mips_tb2/cache/code_miss
add wave -noupdate -group I-Cache -format Literal -radix hexadecimal /mips_tb2/cache/code_refill_addr
add wave -noupdate -group I-Cache -format Literal -radix hexadecimal /mips_tb2/cache/code_rd_addr_reg
add wave -noupdate -group D-Cache
add wave -noupdate -format Literal -radix hexadecimal /mips_tb2/cache/bram_rd_addr
add wave -noupdate -format Literal -radix hexadecimal /mips_tb2/cache/bram_rd_data
add wave -noupdate -expand -group D-Cache
add wave -noupdate -group D-Cache -format Literal -radix unsigned /mips_tb2/cache/data_line_addr
add wave -noupdate -group D-Cache -format Literal /mips_tb2/cache/data_refill_ctr
add wave -noupdate -group D-Cache -format Literal -radix hexadecimal /mips_tb2/cache/data_refill_data
add wave -noupdate -group D-Cache -format Logic /mips_tb2/cache/data_miss
add wave -noupdate -group D-Cache -format Logic /mips_tb2/cache/data_miss_cached
add wave -noupdate -group D-Cache -format Logic /mips_tb2/cache/data_miss_uncached
add wave -noupdate -group D-Cache -format Logic /mips_tb2/cache/data_wait
add wave -noupdate -group D-Cache -color {Forest Green} -format Logic /mips_tb2/cache/read_pending
add wave -noupdate -group D-Cache -color Khaki -format Logic /mips_tb2/cache/write_pending
add wave -noupdate -group D-Cache -format Literal -radix hexadecimal /mips_tb2/cache/data_cache_store
add wave -noupdate -group STALL
add wave -noupdate -group STALL -format Logic /mips_tb2/cpu/stalled_interlock
add wave -noupdate -group STALL -format Logic /mips_tb2/cpu/stalled_memwait
add wave -noupdate -group STALL -format Logic /mips_tb2/cpu/stalled_muldiv
add wave -noupdate -group DRAM
add wave -noupdate -group DRAM -color Tan -format Literal /mips_tb2/cache/byte_we
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2710000 ps} 0}
WaveRestoreCursors {{Cursor 3} {332910000 ps} 0} {{Cursor 4} {333210000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 64
configure wave -justifyvalue left
62,4 → 71,4
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {2668953 ps} {2884729 ps}
WaveRestoreZoom {2730493199 ps} {2730847727 ps}

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