URL
https://opencores.org/ocsvn/ion/ion/trunk
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- This comparison shows the changes necessary to convert path
/ion/trunk/src/memtest
- from Rev 213 to Rev 229
- ↔ Reverse comparison
Rev 213 → Rev 229
/memtest.s
41,10 → 41,11
#---- UART stuff |
.set UART_BASE, 0x20000000 # UART base address |
.set UART_TX, 0x0000 # TX reg offset |
.set UART_STATUS, 0x0020 # status reg offset |
.set UART_STATUS, 0x0004 # status reg offset |
.set UART_TX_RDY, 0x0001 # tx ready flag mask |
|
#---- Debug register block -- 4 read-write, 32-bit registers |
.set DEBUG_BASE, 0x2000f000 # Debug block base |
.set DEBUG_BASE, 0x20010020 # Debug block base |
|
#--------------------------------------------------------------------------- |
|
396,11 → 397,26
blt $a2,$a1,inv_i_cache_loop |
addi $a2,1 |
|
# Now, the D-Cache is different. To invalidate a D-Cache line you just |
# read from it (by proper selection of a dummy target address) while bits |
# CP0[12].17:16=01. The data read is undefined and should be discarded. |
|
li $a0,0 # Use any base address that is mapped |
li $a2,0 |
li $a1,DCACHE_NUM_LINES-1 |
|
inv_d_cache_loop: |
lw $zero,0($a0) |
addi $a0,DCACHE_LINE_SIZE*4 |
blt $a2,$a1,inv_d_cache_loop |
addi $a2,1 |
|
lui $a1,0x0002 # Leave with cache enabled |
mfc0 $a0,$12 |
li $a1,0x00020000 # Leave cache enabled |
or $a0,$a0,$a1 |
andi $a0,$a0,0xffff |
or $a1,$a0,$a1 |
jr $ra |
mtc0 $a0,$12 |
mtc0 $a1,$12 |
|
|
|
420,7 → 436,7
addiu $a0,1 |
puts_wait_tx_rdy: |
lw $v1,UART_STATUS($a2) |
andi $v1,$v1,0x02 |
andi $v1,$v1,UART_TX_RDY |
beqz $v1,puts_wait_tx_rdy |
nop |
sw $v0,UART_TX($a2) |
446,7 → 462,7
lb $v0,0($s2) |
put_hex_wait_tx_rdy: |
lw $v1,UART_STATUS($a2) |
andi $v1,$v1,0x02 |
andi $v1,$v1,UART_TX_RDY |
beqz $v1,put_hex_wait_tx_rdy |
nop |
sw $v0,UART_TX($a2) |
/readme.txt
10,4 → 10,6
unprogrammed you will skip the final part of the test (execution from 8-bit |
static memory). |
|
|
Note that the very first test, "Testing D-Cache with back-to-back pairs of RD & |
WR cycles" WILL fail in the hardware demo because it relies on debug registers |
only present in the simulation test bench. |
/makefile
4,12 → 4,16
# We'll run the simulation for long enough to complete the test |
SIM_LENGTH = 400000 |
|
# FPGA Block RAM parameters |
# FPGA Block RAM parameters (size in words) |
BRAM_START = 0xbfc00000 |
CODE_BRAM_SIZE = 2048 |
# Simulated FLASH parameters (size in bytes) |
FLASH_START = 0xb0000000 |
# External RAM parameters (size in words) |
XRAM_SIZE = 1024 |
FLASH_SIZE = 4096 |
# External RAM parameters (size in 16-bit halfwords) |
# This is the RAM size simulated by slite; set the same value so the execution |
# logs match. |
XRAM_SIZE = 2048 |
XRAM_START = 0x00000000 |
# Set to > 0 to initialize and enable the cache before running the tests |
TEST_CACHE = 1 |
66,26 → 70,23
|
#-- Targets that build the synthesizable vhdl; meant for direct invocation ----- |
|
# Create VHDL file for simulation test bench using TB2 template |
#-- Create VHDL package with data and parameters for simulation |
sim: memtest demo |
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \ |
--flash flash.bin --flash_size 4096 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \ |
-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2 |
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \ |
--flash flash.bin --flash_size 4096 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \ |
-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2 |
$(VHDL_OBJ_PKG) --project="Memtest" \ |
--package sim_params_pkg \ |
--bin memtest.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \ |
--bin memtest.data --name sram_init --xram_size $(XRAM_SIZE) \ |
--bin flash.bin --name prom_init --flash_size $(FLASH_SIZE) \ |
--output $(TB_DIR)/sim_params_pkg.vhdl \ |
-s $(SIM_LENGTH) --log_trigger=0xbfc00000 \ |
|
|
# Create VHDL file for hardware demo |
#-- Create VHDL package with data and parameters for syntesis |
demo: memtest |
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xb0000000 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-v $(SRC_DIR)/code_rom_template.vhdl -n "Memory test" \ |
-o $(DEMO_DIR)/code_rom_pkg.vhdl |
$(VHDL_OBJ_PKG) --project="Memtest" \ |
--package obj_code_pkg \ |
--bin memtest.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \ |
--output $(DEMO_DIR)/../SoC/bootstrap_code_pkg.vhdl |
|
|
#-- And now the usual housekeeping stuff --------------------------------------- |
/flash.s
32,7 → 32,8
#---- UART stuff |
.set UART_BASE, 0x20000000 # UART base address |
.set UART_TX, 0x0000 # TX reg offset |
.set UART_STATUS, 0x0020 # status reg offset |
.set UART_STATUS, 0x0004 # status reg offset |
.set UART_TX_RDY, 0x0001 # tx ready flag mask |
|
#--------------------------------------------------------------------------- |
|
253,7 → 254,7
addiu $a0,1 |
puts_wait_tx_rdy: |
lw $v1,UART_STATUS($a2) |
andi $v1,$v1,0x02 |
andi $v1,$v1,UART_TX_RDY |
beqz $v1,puts_wait_tx_rdy |
nop |
sw $v0,UART_TX($a2) |
279,7 → 280,7
lb $v0,0($s2) |
put_hex_wait_tx_rdy: |
lw $v1,UART_STATUS($a2) |
andi $v1,$v1,0x02 |
andi $v1,$v1,UART_TX_RDY |
beqz $v1,put_hex_wait_tx_rdy |
nop |
sw $v0,UART_TX($a2) |