URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
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- This comparison shows the changes necessary to convert path
/ion/trunk/src
- from Rev 192 to Rev 193
- ↔ Reverse comparison
Rev 192 → Rev 193
/hello/makefile
68,12 → 68,17
#-- Targets that build the synthesizable vhdl; meant for direct invocation ----- |
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#-- Create VHDL file for simulation test bench using TB2 template |
sim: hello |
sim: hello demo |
$(TO_VHDL) --code hello.code --data hello.data \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
--log_trigger=0xbfc00000 \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb2_template.vhdl \ |
-o $(TB_DIR)/mips_tb2.vhdl -e mips_tb2 |
$(TO_VHDL) --code hello.code --data hello.data \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
--log_trigger=0xbfc00000 \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \ |
-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2 |
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#-- Create VHDL file for simulation test bench using TB0 template |
sim_bram: hello |
/opcodes/makefile
32,9 → 32,14
sim: opcodes |
$(TO_VHDL) --code opcodes.bin --data opcodes.data --log_trigger=0xbfc00000 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(DATA_BRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \ |
-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2 |
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \ |
-o $(TB_DIR)\\sim_params_pkg.vhdl -e dummy -n "Opcode tester" |
$(TO_VHDL) --code opcodes.bin --data opcodes.data --log_trigger=0xbfc00000 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-v $(SRC_DIR)/code_rom_template.vhdl -n "Opcode tester" \ |
-o $(DEMO_DIR)/code_rom_pkg.vhdl |
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#-- And now the usual housekeeping stuff --------------------------------------- |
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/adventure/makefile
103,12 → 103,17
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# Create VHDL file for simulation test bench using TB2 template |
sim: bootstrap adventure |
sim: bootstrap adventure demo |
$(TO_VHDL) --code bootstrap.code --log_trigger=b0000000 \ |
--flash adventure.bin --flash_size $(FLASH_SIM_SIZE) \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \ |
-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2 |
-o $(TB_DIR)\\mips_tb2.vhdl -e dummy -n "Adventure" |
$(TO_VHDL) --code bootstrap.code --log_trigger=b0000000 \ |
--flash adventure.bin --flash_size $(FLASH_SIM_SIZE) \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)\\sim_params_template.vhdl \ |
-o $(TB_DIR)\\sim_params_pkg.vhdl -e dummy -n "Adventure" |
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# Create VHDL file for hardware demo |
/memtest/makefile
66,12 → 66,17
#-- Targets that build the synthesizable vhdl; meant for direct invocation ----- |
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# Create VHDL file for simulation test bench using TB2 template |
sim: memtest |
sim: memtest demo |
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \ |
--flash flash.bin --flash_size 4096 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \ |
-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2 |
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \ |
--flash flash.bin --flash_size 4096 \ |
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \ |
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \ |
-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2 |
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# Create VHDL file for hardware demo |