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Rev 196 → Rev 197

/hello/readme.txt
3,5 → 3,5
 
See makefile for targets, etc.
 
This program can be simulated with TB2 and can be built into a hardware
demo.
Can be simulated (both Modelsim and SW simulator) and synthesized to a hardware
demo (see makefiles).
/readme.txt
13,23 → 13,32
Most makefiles have two targets, to create a simulation test bench and a
synthesizable demo.
 
Target 'sim' will build the simulation test bench as vhdl file
'/vhdl/tb/mips_tb2.vhdl'. This is the default test bench expected by the
simulation script '/sim/mips_tb2.do'.
Target 'sim' will build a the simulation test bench package as vhdl file
'/vhdl/tb/sim_params_pkg.vhdl'. This is the default test bench expected by the
simulation script '/sim/mips_tb.do'. The template used to build the package is
file '/src/sim_params_template.pkg' and the tool used to insert the data into
the template is the python script '/src/bin2hdl.py'.
 
Target 'demo' will build a synthesizable demo as '/vhdl/demo/mips_mpu.vhdl'.
Target 'demo' will build a package for the synthesizable demo as file
'/vhdl/demo/code_rom_pkg.vhdl', from template file '/code_rom_template.vhdl',
using the same python script.
 
The build process will produce a number of binary files that can be run on the
software simulator. A DOS BATCH file has been provided for each sample that
runs the simulator with the proper parameters (swsim.bat).
 
The simulation log produced by the software simulator can be compared to the log
produced by Modelsim (the only hdl simulator supported yet); they should be
identical (but see notes on the project doc).
 
 
 
Support code library:
=====================
 
Many of the code samples use support code from an ad-hoc library included with
the project (src/common/libsoc). Before making any of the samples you should
make the library ('make' with no target). That will build file
make the library ('make' with no target). That command will build lib file
'src/common/libsoc/libsoc.a'.
 
 
43,5 → 52,6
 
python bin2hdl.py --help
 
to get a short description.
There's a more detailed description in the project main doc.
to get a short description and usage instructions.
There's a more detailed description in the project main doc (Well, I hope there
is one by the time you read this, documentation has been falling behind lately).
/opcodes/readme.txt
1,27 → 1,10
This is a basic opcode test bench which tries all supported opcodes. See the
source comments. This code has been lifted whole from the Plasma project.
source comments. This code has been lifted whole from the Plasma project and
then gradually modified to its present state.
 
Build the program with:
This program can be simulated (both Modelsim and SW simulator) but it can't be
synthesized to a hardware demo (see makefiles). Only a 'sim' target is provided
in the makefile.
 
make opcodes
or
make opcodes_sim
 
Read ../readme.txt for some warnings on the makefile configuration.
 
 
It will build a vhdl test bench at /vhdl/tb/mips_tb2.vhdl (overwriting) that you
can try on your VHDL simulator with script sim_tb2.do. The provided script and
the VHDL code have some dependence on Modelsim, see project readme file.
 
 
The makefile will too bouild some bionaries that you can run in the software
simulator:
 
slite --bram=opcodes.bin --xram=opcodes.data
 
 
This code can't be used on real hardware (i/o is far too simple).
 
WARNING: the gnu assembler expands DIV* instructions, inserting code that
handles division by zero. Bear that in mind when reading the listing file.
/memtest/readme.txt
1,8 → 1,13
This code sample tests access to external (off-FPGA) memory, including both
16-bit SRAM and 8-bit FLASH present in the DE-1 board.
 
Can be simulated (both Modelsim and SW simulator) and synthesized to a hardware
demo (see makefiles).
 
File flash.bin is meant to be loaded at the start of the flash of the DE-1
board using the altera tools provided for that purpose. This program will
board using the Altera/Terasic tool provided for that purpose. This program will
eventually jump to flash (see the sources and makefile) so if you leave it
unprogrammed you will skip the final part of the test (execution from 8-bit
static memory).
 
 

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