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URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

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  • This comparison shows the changes necessary to convert path 
    /ion/trunk/vhdl
    from Rev 194 to Rev 200
    ↔ Reverse comparison
  •

Rev 194 → Rev 200

/demo/mips_mpu.vhdl
40,7 → 40,7
port(
clk : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
interrupt : in std_logic_vector(7 downto 0);
-- interface to FPGA i/o devices
io_rd_data : in std_logic_vector(31 downto 0);
114,7 → 114,7
 
cpu: entity work.mips_cpu
port map (
interrupt => '0',
interrupt => interrupt,
data_addr => cpu_data_addr,
data_rd_vma => cpu_data_rd_vma,
/demo/c2sb_demo.vhdl
228,7 → 228,7
SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
)
port map (
interrupt => '0',
interrupt => "00000000",
 
-- interface to FPGA i/o devices
io_rd_data => io_rd_data,
/tb/mips_tb.vhdl
95,6 → 95,8
signal rxd : std_logic;
signal txd : std_logic;
 
-- Other CPU signals
signal cpu_irq : std_logic_vector(7 downto 0);
 
--------------------------------------------------------------------------------
-- Logging signals
109,10 → 111,18
-- All the info needed by the logger is here
signal log_info : t_log_info;
 
-- Debug signals ---------------------------------------------------------------
-- IRQ trigger simulation ------------------------------------------------------
 
signal irq_trigger_addr : std_logic_vector(2 downto 0);
signal irq_trigger_data : std_logic_vector(31 downto 0);
signal irq_trigger_load : std_logic;
 
subtype t_irq_countdown is std_logic_vector(31 downto 0);
type t_irq_countdown_array is array(0 to 7) of t_irq_countdown;
 
signal irq_countdown : t_irq_countdown_array;
 
 
begin
 
-- UUT instantiation -------------------------------------------------------
122,7 → 132,7
SRAM_ADDR_SIZE => 32
)
port map (
interrupt => '0',
interrupt => cpu_irq(0),
 
-- interface to FPGA i/o devices
io_rd_data => io_rd_data,
231,8 → 241,57
 
-- Simulate dummy I/O traffic external to the MCU --------------------------
-- FIXME console logging missing! IO too!
-- the only IO present is the test interrupt trigger registers
simulated_io:
process(clk)
variable i : integer;
variable uart_data : integer;
begin
if clk'event and clk='1' then
if io_byte_we /= "0000" then
if io_wr_addr(31 downto 16)=X"2001" then
irq_trigger_load <= '1';
irq_trigger_data <= io_wr_data;
irq_trigger_addr <= io_wr_addr(4 downto 2);
else
irq_trigger_load <= '0';
end if;
else
irq_trigger_load <= '0';
end if;
end if;
end process simulated_io;
-- Simulate IRQs -----------------------------------------------------------
irq_trigger_registers:
process(clk)
variable index : integer range 0 to 7;
begin
if clk'event and clk='1' then
if reset='1' then
cpu_irq <= "00000000";
else
if irq_trigger_load='1' then
index := conv_integer(irq_trigger_addr);
irq_countdown(index) <= irq_trigger_data;
else
for index in 0 to 7 loop
if irq_countdown(index) = X"00000001" then
cpu_irq(index) <= '1';
irq_countdown(index) <= irq_countdown(index) - 1;
elsif irq_countdown(index)/=X"00000000" then
irq_countdown(index) <= irq_countdown(index) - 1;
cpu_irq(index) <= '0';
else
cpu_irq(index) <= '0';
end if;
end loop;
end if;
end if;
end if;
end process irq_trigger_registers;
 
-- This is useless (the simulated UART will not be actually used)
-- but at least prevents the simulator from optimizing the logic away.
rxd <= txd;
248,6 → 307,5
LOG_TRIGGER_ADDRESS, log_file, con_file);
wait;
end process log_execution;
 
end architecture testbench;
/mips_cpu.vhdl
4,7 → 4,7
-- project: ION (http://www.opencores.org/project,ion_cpu)
-- author: Jose A. Ruiz (ja_rd@hotmail.com)
-- created: Jan/11/2011
-- last modified: Jun/05/2011 (ja_rd@hotmail.com)
-- last modified: Jul/31/2011 (ja_rd@hotmail.com)
--------------------------------------------------------------------------------
-- Please read file /doc/ion_project.txt for usage instructions.
--------------------------------------------------------------------------------
19,16 → 19,13
-- if the target register is not used in the following instruction. So that
-- every load takes two cycles.
-- The interlock logic should check register indices (@note2)
-- 2.- CP0 SR (status register) bits KUo/IEo & KUP/IEp are missing.
-- This means that EXCEPTIONS CAN'T BE NESTED in this version of the CPU.
-- 3.- Invalid instruction side effects:
-- 2.- Invalid instruction side effects:
-- Invalid opcodes do trap but the logic that prevents bad opcodes from
-- having side affects has not been tested yet.
-- 4.- Kernel/user status.
-- 3.- Kernel/user status.
-- When in user mode, COP* instructions will trigger a 'CpU' exception.
-- BUT there's no address checking and user code can still access kernel
-- space in this version.
-- Besides, see point 2 above about the missing SR bits.
--
--------------------------------------------------------------------------------
-- KNOWN BUGS:
35,7 → 32,7
--
-- 1.- The instruction executed right after entering user mode (i.e. the
-- instruction after the MTC0 or RFE that clears the KU flag) is executed
-- in kernel mode (instead of user mode). This is a gapping security hole,
-- in kernel mode (instead of user mode). This is a gaping security hole,
-- in case it makes any sense to speak of security in this project at this
-- stage.
-- This can be easily fixed but is not very urgent.
82,7 → 79,7
port(
clk : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
interrupt : in std_logic_vector(7 downto 0);
 
data_addr : out std_logic_vector(31 downto 0);
 

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