URL
https://opencores.org/ocsvn/ion/ion/trunk
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- This comparison shows the changes necessary to convert path
/ion/trunk/vhdl
- from Rev 207 to Rev 211
- ↔ Reverse comparison
Rev 207 → Rev 211
/tb/mips_tb.vhdl
128,7 → 128,11
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signal irq_countdown : t_irq_countdown_array; |
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-- Simulated block of 4 read/write, 32-bit I/O registers, used in cache test. |
type t_debug_reg_block is array(0 to 3) of t_word; |
signal debug_reg_block : t_debug_reg_block; |
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begin |
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-- UUT instantiation ------------------------------------------------------- |
256,9 → 260,13
if clk'event and clk='1' then |
if io_byte_we /= "0000" then |
if io_wr_addr(31 downto 16)=X"2001" then |
-- IRQ trigger register block (write only) |
irq_trigger_load <= '1'; |
irq_trigger_data <= io_wr_data; |
irq_trigger_addr <= io_wr_addr(4 downto 2); |
elsif io_wr_addr(31 downto 12)=X"2000f" then |
-- Debug register block (read/write) |
debug_reg_block(conv_integer(unsigned(io_wr_addr(3 downto 2)))) <= io_wr_data; |
else |
irq_trigger_load <= '0'; |
end if; |
268,6 → 276,10
end if; |
end process simulated_io; |
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-- The only readable i/o is the debug reg block. We simulate an asynchronous |
-- read port (a mux). |
io_rd_data <= debug_reg_block(conv_integer(unsigned(io_rd_addr(3 downto 2)))); |
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-- Simulate IRQs ----------------------------------------------------------- |
irq_trigger_registers: |
process(clk) |