URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
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- This comparison shows the changes necessary to convert path
/ion/trunk
- from Rev 147 to Rev 148
- ↔ Reverse comparison
Rev 147 → Rev 148
/src/opcodes/makefile
3,7 → 3,7
include ../common/makefile |
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# We'll run the simulation for long enough for the program to finish |
SIM_LENGTH = 70000 |
SIM_LENGTH = 140000 |
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# FPGA Block RAM parameters |
BRAM_START = 0xbfc00000 |
/src/opcodes/opcodes.s
34,6 → 34,11
# WARNING: the assembler expands div instructions, see 'as' manual |
.set TEST_DIV, 1 # DIV* instructions |
.set TEST_MUL, 1 # MUL* instructions |
.set USE_CACHE, 1 # Initialize and enable cache |
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.set ICACHE_NUM_LINES, 256 # no. of lines in the I-Cache |
.set DCACHE_NUM_LINES, 256 # no. of lines in the D-Cache |
.set DCACHE_LINE_SIZE, 4 # D-Cache line size in words |
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#--------------------------------------------------------------------------- |
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109,7 → 114,12
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StartTest: |
.ifgt USE_CACHE |
jal setup_cache |
nop |
.else |
mtc0 $0,$12 # disable interrupts, disable cache |
.endif |
lui $20,0x2000 # serial port write address |
ori $21,$0,'\n' # <CR> character |
ori $22,$0,'X' # 'X' letter |
1393,13 → 1403,48
ori $v0,0x5503 |
test_b11: |
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$DONE: |
j $DONE |
nop |
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# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM) |
setup_cache: |
lui $a0,0x0001 # Enable I-cache line invalidation |
mtc0 $a0,$12 |
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# In order to invalidate a I-Cache line we have to write its tag number to |
# any address while bits CP0[12].17:16=01. The write will be executed as a |
# regular write too, as a side effect, so we need to choose a harmless |
# target address. The BSS will do -- it will be cleared later. |
# We'll cover all ICACHE_NUM_LINES lines no matter what the starting |
# address is, anyway. |
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la $a0,__bss_start |
li $a2,0 |
li $a1,ICACHE_NUM_LINES-1 |
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inv_i_cache_loop: |
sw $a2,0($a0) |
blt $a2,$a1,inv_i_cache_loop |
addi $a2,1 |
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# Now, the D-Cache is different. To invalidate a D-Cache line you just |
# read from it (by proper selection of a dummy target address) while bits |
# CP0[12].17:16=01. The data read is undefined and should be discarded. |
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li $a0,0 # Use any base address that is mapped |
li $a2,0 |
li $a1,DCACHE_NUM_LINES-1 |
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inv_d_cache_loop: |
lw $zero,0($a0) |
addi $a0,DCACHE_LINE_SIZE*4 |
blt $a2,$a1,inv_d_cache_loop |
addi $a2,1 |
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lui $a1,0x0002 # Leave with cache enabled |
jr $ra |
mtc0 $a1,$12 |
.set reorder |
.end entry |
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