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Tools

URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

Compare Revisions

This comparison shows the changes necessary to convert path
```
/ion/trunk
```
from Rev 156 to Rev 157
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 156 → Rev 157

/vhdl/tb/mips_tb_pkg.vhdl

61,6 → 61,7

cp0_cache_control : std_logic_vector(1 downto 0);

prev_status : t_word;

p1_set_cp0 : std_logic;

p1_rfe : std_logic;

pc_mtc0 : t_word;

pc_m : t_pc_queue;

260,7 → 261,7

         -- CP0, register SR
         -- If SR changed by mtc0 instruction, get the mtc0 address
-        if info.p1_set_cp0='1' and info.cp0_status(1)='1' then
+        if (info.p1_set_cp0='1' or info.p1_rfe='1') and info.cp0_status(1)='1' then
             info.pc_mtc0 <= info.pc_m(k-1);
         end if;

354,6 → 355,7

init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);

init_signal_spy("/"&entity_name&"/cp0_status", signal_name&".cp0_status", 0, -1);

init_signal_spy("/"&entity_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0, -1);

init_signal_spy("/"&entity_name&"/p1_rfe", signal_name&".p1_rfe", 0, -1);

init_signal_spy("/"&entity_name&"/cp0_cache_control", signal_name&".cp0_cache_control", 0, -1);

init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);

init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);

/vhdl/mips_cpu.vhdl

213,6 → 213,7

-- CP0[12]: status register, KUo/IEo & KUP/IEp & KU/IE bits

signal cp0_status : std_logic_vector(5 downto 0);

signal cp0_sr_ku_reg : std_logic;

-- CP0[12]: status register, cache control

signal cp0_cache_control : std_logic_vector(17 downto 16);

-- Output of CP0 register bank (only a few regs are implemented)

793,7 → 794,9

     (p1_set_cp='1' and p1_set_cp0='0') or   -- mtc1..3
     (p1_get_cp='1' and p1_get_cp0='0') or   -- mfc1..3
     ((p1_get_cp0='1' or p1_set_cp0='1' or p1_rfe='1')
-                     and cp0_status(1)='0') -- COP0 user mode
+                     and cp0_sr_ku_reg='0')
+                     --and cp0_status(1)='0') -- COP0 user mode
+    -- FIXME CP1..3 logic missing
     else '0';
 --##############################################################################

1036,6 → 1039,7

if reset='1' then

-- KU/IE="10" ==> mode=kernel; ints=disabled

cp0_status <= "000010"; -- bits (KUo/IEo & KUp/IEp) reset to zero

cp0_sr_ku_reg <= '1'; -- delayed KU flag

cp0_cache_control <= "00";

cp0_cause_exc_code <= "00000";

cp0_cause_bd <= '0';

1068,7 → 1072,6

-- ... and the BD flag for exceptions in delay slots

cp0_cause_bd <= cp0_in_delay_slot;

-- FIXME RFE missing

elsif p1_rfe='1' and cp0_status(1)='1' then

-- RFE: restore ('pop') the KU/IE flag values

1085,6 → 1088,9

                     cp0_cache_control <= p1_rt(17 downto 16);
                 end if;
             end if;
+            if stall_pipeline='0' then
+                cp0_sr_ku_reg <= cp0_status(1);
+            end if;
         end if;
     end if;
 end process cp0_registers;