URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
Compare Revisions
- This comparison shows the changes necessary to convert path
/ion/trunk
- from Rev 160 to Rev 161
- ↔ Reverse comparison
Rev 160 → Rev 161
/src/mips_mpu1_template.vhdl
8,6 → 8,29
-- to test external memory interface and cache-cpu interface without the cache |
-- functionality getting in the way. |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/src/mips_tb0_template.vhdl
21,6 → 21,29
-- |
-- WARNING: Will only work on Modelsim; uses custom library SignalSpy. |
--############################################################################## |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
--############################################################################## |
|
library ieee; |
use ieee.std_logic_1164.all; |
/src/mips_tb2_template.vhdl
22,6 → 22,29
-- |
-- WARNING: Will only work on Modelsim; uses custom library SignalSpy. |
--############################################################################## |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
--############################################################################## |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vhdl/demo/rs232_rx.vhdl
4,6 → 4,29
-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing! |
-- I don't advise using this in for any general purpose. |
--############################################################################## |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
--############################################################################## |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vhdl/demo/rs232_tx.vhdl
4,6 → 4,29
-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing! |
-- I don't advise using this in for any general purpose. |
--############################################################################## |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
--############################################################################## |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vhdl/demo/c2sb_demo.vhdl
6,6 → 6,29
-------------------------------------------------------------------------------- |
-- NOTE: See note at bottom of file about optional use of PLL. |
--############################################################################## |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
--############################################################################## |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vhdl/mips_alu.vhdl
1,3 → 1,31
-------------------------------------------------------------------------------- |
-- mips_alu.vhdl -- integer arithmetic ALU, excluding mult/div functionality. |
-- |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
12,18 → 40,8
|
-- function selection |
ac : in t_alu_control; |
|
flags : out t_alu_flags; |
|
-- '1' when inp1 is zero |
--flags.inp1_eq_zero : out std_logic; |
-- '1' when inp1 is < 0 (bit 31 set) |
--flags.inp1_lt_zero : out std_logic; |
-- '1' when (inp1 + ac.neg_sel(inp2) + ac.cy_in) < 0 |
--flags.inp1_lt_inp2 : out std_logic; |
-- '1' when (inp1 + ac.neg_sel(inp2) + ac.cy_in) == 0 |
--flags.inp1_eq_inp2 : out std_logic; |
|
-- comparison result flags |
flags : out t_alu_flags; |
-- data inputs |
inp1 : in std_logic_vector(31 downto 0); |
inp2 : in std_logic_vector(31 downto 0); |
/vhdl/mips_pkg.vhdl
10,6 → 10,29
-- new IO registers). |
-- Please see the module c2sb_demo and mips_mcu for examples of memory decoding. |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vhdl/sdram_controller.vhdl
1,12 → 1,9
--############################################################################## |
-------------------------------------------------------------------------------- |
-- sdram_controller.vhdl -- Interface for 16-bit SDRAM (non-DDR). |
-- |
-- This module has been tested with a PSC A2V64S40 chip (equivalent to ISSI's |
-- IS42S16400). Many parameters are still hardcoded (see below) including the |
-- number of banks. |
-- |
-- |
-- |
-------------------------------------------------------------------------------- |
-- To Be Done: |
-- 1) CL and BL are hardcoded, generics are ignored. |
14,9 → 11,31
-- 3) Auto-refresh logic is missing. |
-- 4) No. of banks is hardcoded to 4. |
-- |
--############################################################################## |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
/vhdl/mips_cache.vhdl
141,6 → 141,29
-- it would be better to insert an extra cycle after the wait states in |
-- the sram read state machine. |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vhdl/mips_shifter.vhdl
1,6 → 1,31
--------------------------------------------------------------------- |
-------------------------------------------------------------------------------- |
-- mips_shifter.vhdl -- combinational barrel shifter |
-- |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
--------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
38,6 → 63,8
-- The barrel shifter can account for as much as 1/4 of the CPU area |
-- (excluding mult/div unit) so it makes sense to be cheap here if what we |
-- want is a small core. |
-- NOTE: this logic may or may not be in the critical delay path of the |
-- core, depending on the cache implementation. See your synthesis report. |
|
-- Reverse input when shifting right |
input_reversed: |
/vhdl/mips_cpu.vhdl
6,10 → 6,6
-- created: Jan/11/2011 |
-- last modified: Jun/05/2011 (ja_rd@hotmail.com) |
-------------------------------------------------------------------------------- |
-- Use under the terms of the GPL. |
-- Software 'as is' without warranty. Author liable for nothing. |
-- |
-------------------------------------------------------------------------------- |
-- Please read file /doc/ion_project.txt for usage instructions. |
-------------------------------------------------------------------------------- |
--### MIPS-I things not implemented |
37,10 → 33,36
-------------------------------------------------------------------------------- |
-- KNOWN BUGS: |
-- |
-- 1.- The instruction after entering user mode (i.e. the instruction after the |
-- MTC0 or RFE that clears the KU flag) is executed in kernel mode. |
-- 1.- The instruction executed right after entering user mode (i.e. the |
-- instruction after the MTC0 or RFE that clears the KU flag) is executed |
-- in kernel mode (instead of user mode). This is a gapping security hole, |
-- in case it makes any sense to speak of security in this project at this |
-- stage. |
-- This can be easily fixed but is not very urgent. |
-------------------------------------------------------------------------------- |
-- Copyright (C) 2010 Jose A. Ruiz |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |