URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
Compare Revisions
- This comparison shows the changes necessary to convert path
/ion/trunk
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/src/mips_tb0_template.vhdl
1,14 → 1,19
--############################################################################## |
-- This file was generated automatically from '/src/mips_tb0_template.vhdl'. |
-- |
-- Simulates the CPU core connected to two memory block, a read-only block |
-- initialized with code and a read-write block initialized with all data, |
-- including read-only data. The makefile for the source samples include targets |
-- to build simulation test benches using this template. |
-------------------------------------------------------------------------------- |
-- Simulation test bench TB0 -- not synthesizable. |
-- |
-- The memory setup is meant to test the 'bare' cpu, without cache. |
-- Simulates the CPU core connected to a single memory block initialized with |
-- the program object code and (initialized) data. The makefile for the source |
-- samples include targets to build simulation test benches using this template. |
-- |
-- The memory setup is meant to test the 'bare' cpu, without cache and with |
-- all object code in a single 3-port memory block. |
-- Address decoding is harcoded to that of Plasma system, for the time being. |
-- |
-- Console output (at addresses compatible to Plasma's) is logged to text file |
-- "hw_sim_console_log.txt". |
-- IMPORTANT: The code that echoes UART TX data to the simulation console does |
-- line buffering; it will not print anything until it gets a CR (0x0d), and |
-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you |
/src/mips_tb1_template.vhdl
1,16 → 1,20
--############################################################################## |
-- This file was generated automatically from '/src/mips_tb1_template.vhdl'. |
-- |
-- Simulates the CPU core connected to two memory block, a read-only block |
-- |
-------------------------------------------------------------------------------- |
-- Simulation test bench TB1 -- not synthesizable. |
-- |
-- Simulates the CPU core connected to two memory blocks, a read-only block |
-- initialized with code and a read-write block initialized with all data, |
-- including read-only data. The makefile for the source samples include targets |
-- to build simulation test benches using this template. |
-- to build simulation test benches using this template -- those source samples |
-- that support this template. |
-- |
-- The memory setup is meant to test the 'bare' cpu, without cache. |
-- |
-- Address decoding is harcoded to that of Plasma system, for the time being. |
-- |
-- |
-- Console output (at addresses compatible to Plasma's) is logged to text file |
-- "hw_sim_console_log.txt". |
-- IMPORTANT: The code that echoes UART TX data to the simulation console does |
-- line buffering; it will not print anything until it gets a CR (0x0d), and |
-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you |
/src/opcodes/opcodes.s
16,8 → 16,8
# |
#------------------------------------------------------------------------------- |
# NOTE: This test bench relies on the simulation logs to catch errors. That is, |
# unlike the original Plasma code, this one does not test the test success |
# conditions. instead, it performs the operations to be tested and relies on you |
# unlike the original Plasma code, this one does not check the test success |
# conditions. Instead, it performs the operations to be tested and relies on you |
# to compare the logs from the logic simulation and the software simulation. |
# Test that work this way have been commented with this tag: "@log" |
# |
1211,8 → 1211,8
sb $2,0($20) |
sb $23,0($20) |
sb $21,0($20) |
|
|
|
$DONE: |
j $DONE |
nop |