URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
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- This comparison shows the changes necessary to convert path
/ion
- from Rev 101 to Rev 102
- ↔ Reverse comparison
Rev 101 → Rev 102
/trunk/src/mips_mpu1_template.vhdl
57,7 → 57,10
signal cpu_data_wr : t_word; |
signal cpu_byte_we : std_logic_vector(3 downto 0); |
signal cpu_mem_wait : std_logic; |
signal cpu_ic_invalidate : std_logic; |
signal cpu_cache_enable : std_logic; |
|
|
-- interface to i/o |
signal mpu_io_rd_data : std_logic_vector(31 downto 0); |
signal mpu_io_wr_data : std_logic_vector(31 downto 0); |
119,6 → 122,8
byte_we => cpu_byte_we, |
|
mem_wait => cpu_mem_wait, |
cache_enable=> cpu_cache_enable, |
ic_invalidate=>cpu_ic_invalidate, |
|
clk => clk, |
reset => reset |
146,7 → 151,8
data_wr => cpu_data_wr, |
|
mem_wait => cpu_mem_wait, |
cache_enable => '1', |
cache_enable => cpu_cache_enable, |
ic_invalidate => cpu_ic_invalidate, |
|
-- interface to FPGA i/o devices |
io_rd_data => mpu_io_rd_data, |
/trunk/src/mips_tb2_template.vhdl
48,8 → 48,7
-- WARNING: slite does not simulate this. The logs may be different when > 0.0! |
constant SIMULATED_UART_TX_TIME : time := 0.0 us; |
|
-- Simulation length in clock cycles |
-- 2000 is enough for 'hello' sample, 22000 enough for 10 digits of pi |
-- Simulation length in clock cycles, should be long enough (you have to try...) |
constant SIMULATION_LENGTH : integer := @sim_len@; |
|
-- Simulated external SRAM size in 32-bit words |
138,6 → 137,8
signal cpu_data_wr : t_word; |
signal cpu_byte_we : std_logic_vector(3 downto 0); |
signal cpu_mem_wait : std_logic; |
signal cpu_ic_invalidate : std_logic; |
signal cpu_cache_enable : std_logic; |
|
-- interface to i/o |
signal io_rd_data : std_logic_vector(31 downto 0); |
194,6 → 195,8
byte_we => cpu_byte_we, |
|
mem_wait => cpu_mem_wait, |
cache_enable=> cpu_cache_enable, |
ic_invalidate=>cpu_ic_invalidate, |
|
clk => clk, |
reset => reset |
200,7 → 203,7
); |
|
|
cache: entity work.mips_cache_stub |
cache: entity work.mips_cache |
generic map ( |
BRAM_ADDR_SIZE => BRAM_ADDR_SIZE, |
SRAM_ADDR_SIZE => 32,-- we need the full address to decode sram vs flash |
224,7 → 227,8
data_wr => cpu_data_wr, |
|
mem_wait => cpu_mem_wait, |
cache_enable => '1', |
cache_enable => cpu_cache_enable, |
ic_invalidate => cpu_ic_invalidate, |
|
-- interface to FPGA i/o devices |
io_rd_data => io_rd_data, |