OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

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  • This comparison shows the changes necessary to convert path 
    /ion
    from Rev 214 to Rev 215
    ↔ Reverse comparison
  •

Rev 214 → Rev 215

/trunk/vhdl/SoC/bootstrap_code_pkg.vhdl
0,0 → 1,507
--------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- This file contains object code in the form of a VHDL byte table constant.
-- This constant can be used to initialize FPGA memories for synthesis or
-- simulation.
-- Note that the object code is stored as a plain byte table in byte address
-- order. This table knows nothing of data endianess and can be used to
-- initialize 32-, 16- or 8-bit-wide memory -- memory initialization functions
-- can be found in package mips_pkg.
--------------------------------------------------------------------------------
-- Copyright (C) 2012 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mips_pkg.all;
 
package obj_code_pkg is
 
constant obj_code : t_obj_code(0 to 3678) := (
X"10", X"00", X"00", X"7c", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"40", X"1a", X"68", X"00", X"00", X"1a", X"d0", X"82",
X"33", X"5a", X"00", X"1f", X"34", X"1b", X"00", X"08",
X"13", X"5b", X"00", X"09", X"23", X"7b", X"00", X"01",
X"13", X"5b", X"00", X"05", X"23", X"7b", X"00", X"01",
X"17", X"5b", X"00", X"07", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"00", X"a2", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"00", X"72", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"00", X"72", X"00", X"00", X"00", X"00",
X"0b", X"f0", X"00", X"72", X"00", X"00", X"00", X"00",
X"40", X"1b", X"70", X"00", X"40", X"1a", X"68", X"00",
X"00", X"1a", X"d7", X"c2", X"33", X"5a", X"00", X"01",
X"17", X"40", X"00", X"03", X"23", X"7b", X"00", X"04",
X"03", X"60", X"00", X"08", X"00", X"00", X"00", X"00",
X"23", X"7b", X"00", X"04", X"03", X"60", X"00", X"08",
X"42", X"00", X"00", X"10", X"40", X"04", X"60", X"00",
X"30", X"84", X"ff", X"fe", X"40", X"84", X"60", X"00",
X"0f", X"f0", X"00", X"86", X"00", X"00", X"00", X"00",
X"3c", X"04", X"bf", X"c0", X"24", X"84", X"06", X"b4",
X"00", X"80", X"00", X"08", X"00", X"00", X"00", X"00",
X"3c", X"05", X"00", X"01", X"40", X"04", X"60", X"00",
X"30", X"84", X"ff", X"ff", X"00", X"85", X"28", X"25",
X"40", X"85", X"60", X"00", X"24", X"04", X"00", X"00",
X"24", X"06", X"00", X"00", X"24", X"05", X"00", X"ff",
X"ac", X"86", X"00", X"00", X"00", X"c5", X"08", X"2a",
X"14", X"20", X"ff", X"fd", X"20", X"c6", X"00", X"01",
X"24", X"04", X"00", X"00", X"24", X"06", X"00", X"00",
X"24", X"05", X"00", X"ff", X"8c", X"80", X"00", X"00",
X"20", X"84", X"00", X"10", X"00", X"c5", X"08", X"2a",
X"14", X"20", X"ff", X"fc", X"20", X"c6", X"00", X"01",
X"3c", X"05", X"00", X"02", X"40", X"04", X"60", X"00",
X"30", X"84", X"ff", X"ff", X"00", X"85", X"28", X"25",
X"03", X"e0", X"00", X"08", X"40", X"85", X"60", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"3c", X"1b", X"00", X"00", X"27", X"7b", X"00", X"3c",
X"af", X"7d", X"ff", X"f0", X"af", X"7f", X"ff", X"ec",
X"af", X"68", X"ff", X"e8", X"af", X"69", X"ff", X"e4",
X"af", X"6a", X"ff", X"e0", X"03", X"60", X"e8", X"21",
X"40", X"08", X"70", X"00", X"8d", X"1a", X"00", X"00",
X"40", X"1b", X"68", X"00", X"07", X"70", X"00", X"2d",
X"00", X"00", X"00", X"00", X"00", X"1a", X"4e", X"82",
X"39", X"28", X"00", X"1f", X"11", X"00", X"00", X"1f",
X"39", X"28", X"00", X"1c", X"11", X"00", X"00", X"13",
X"00", X"00", X"00", X"00", X"3c", X"08", X"20", X"01",
X"ad", X"1a", X"04", X"00", X"8f", X"aa", X"ff", X"e0",
X"8f", X"a9", X"ff", X"e4", X"8f", X"a8", X"ff", X"e8",
X"8f", X"bf", X"ff", X"ec", X"8f", X"bd", X"ff", X"f0",
X"40", X"1b", X"70", X"00", X"40", X"1a", X"68", X"00",
X"00", X"1a", X"d7", X"c2", X"33", X"5a", X"00", X"01",
X"17", X"40", X"00", X"03", X"23", X"7b", X"00", X"04",
X"03", X"60", X"00", X"08", X"00", X"00", X"00", X"00",
X"23", X"7b", X"00", X"04", X"03", X"60", X"00", X"08",
X"42", X"00", X"00", X"10", X"33", X"5b", X"00", X"3f",
X"3b", X"68", X"00", X"20", X"11", X"00", X"00", X"14",
X"3b", X"68", X"00", X"21", X"11", X"00", X"00", X"1c",
X"00", X"00", X"00", X"00", X"3c", X"08", X"20", X"01",
X"ad", X"1a", X"04", X"00", X"0b", X"f0", X"00", X"b7",
X"00", X"00", X"00", X"00", X"33", X"5b", X"00", X"3f",
X"3b", X"68", X"00", X"00", X"11", X"00", X"00", X"1e",
X"3b", X"68", X"00", X"04", X"11", X"00", X"00", X"29",
X"00", X"00", X"00", X"00", X"3c", X"08", X"20", X"01",
X"ad", X"1a", X"04", X"00", X"0b", X"f0", X"00", X"b7",
X"00", X"00", X"00", X"00", X"8d", X"1a", X"00", X"04",
X"03", X"e0", X"00", X"08", X"00", X"00", X"00", X"00",
X"0f", X"f0", X"01", X"61", X"3c", X"0a", X"80", X"00",
X"00", X"00", X"40", X"21", X"03", X"6a", X"48", X"24",
X"15", X"20", X"00", X"03", X"00", X"0a", X"50", X"42",
X"15", X"40", X"ff", X"fc", X"25", X"08", X"00", X"01",
X"0b", X"f0", X"01", X"17", X"01", X"00", X"d8", X"21",
X"0f", X"f0", X"01", X"61", X"3c", X"0a", X"80", X"00",
X"00", X"00", X"40", X"21", X"03", X"6a", X"48", X"24",
X"11", X"20", X"00", X"03", X"00", X"0a", X"50", X"42",
X"15", X"40", X"ff", X"fc", X"25", X"08", X"00", X"01",
X"0b", X"f0", X"01", X"17", X"01", X"00", X"d8", X"21",
X"0f", X"f0", X"01", X"61", X"00", X"00", X"00", X"00",
X"00", X"1a", X"41", X"82", X"31", X"08", X"00", X"1f",
X"00", X"1a", X"4a", X"c2", X"31", X"29", X"00", X"1f",
X"01", X"09", X"50", X"21", X"00", X"0a", X"50", X"23",
X"25", X"4a", X"00", X"1f", X"01", X"5b", X"d8", X"04",
X"01", X"5b", X"d8", X"06", X"0b", X"f0", X"01", X"17",
X"01", X"1b", X"d8", X"06", X"0f", X"f0", X"01", X"61",
X"00", X"00", X"00", X"00", X"00", X"1a", X"41", X"82",
X"31", X"08", X"00", X"1f", X"00", X"1a", X"4a", X"c2",
X"31", X"29", X"00", X"1f", X"01", X"28", X"48", X"23",
X"00", X"09", X"58", X"23", X"25", X"6b", X"00", X"1f",
X"01", X"1b", X"48", X"04", X"3c", X"0a", X"ff", X"ff",
X"35", X"4a", X"ff", X"ff", X"01", X"6a", X"50", X"04",
X"01", X"6a", X"50", X"06", X"01", X"0a", X"50", X"04",
X"01", X"2a", X"48", X"24", X"01", X"40", X"50", X"27",
X"0f", X"f0", X"01", X"61", X"00", X"1a", X"d1", X"40",
X"00", X"1a", X"d1", X"42", X"03", X"6a", X"d8", X"24",
X"03", X"69", X"d8", X"25", X"0b", X"f0", X"01", X"17",
X"00", X"00", X"00", X"00", X"00", X"1a", X"4c", X"02",
X"31", X"29", X"00", X"1f", X"3c", X"08", X"bf", X"c0",
X"25", X"08", X"04", X"84", X"00", X"09", X"48", X"c0",
X"01", X"09", X"40", X"20", X"01", X"00", X"00", X"08",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"00", X"b7",
X"00", X"00", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"60", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"61", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"62", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"63", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"64", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"65", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"66", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"67", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"af", X"bb", X"ff", X"e8", X"0b", X"f0", X"01", X"1f",
X"af", X"bb", X"ff", X"e4", X"0b", X"f0", X"01", X"1f",
X"af", X"bb", X"ff", X"e0", X"0b", X"f0", X"01", X"1f",
X"37", X"6b", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"6c", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"6d", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"6e", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"6f", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"70", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"71", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"72", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"73", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"74", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"75", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"76", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"77", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"78", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"79", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"7a", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"7b", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"37", X"7c", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"af", X"bb", X"ff", X"ec", X"0b", X"f0", X"01", X"1f",
X"37", X"7e", X"00", X"00", X"0b", X"f0", X"01", X"1f",
X"af", X"bb", X"ff", X"f0", X"af", X"bf", X"00", X"00",
X"00", X"1a", X"dd", X"42", X"33", X"7b", X"00", X"1f",
X"3c", X"08", X"bf", X"c0", X"25", X"08", X"05", X"b4",
X"00", X"1b", X"d8", X"c0", X"01", X"1b", X"40", X"20",
X"01", X"00", X"f8", X"09", X"00", X"00", X"00", X"00",
X"8f", X"bf", X"00", X"00", X"03", X"e0", X"00", X"08",
X"00", X"00", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"34", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"e8", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"e4", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"e0", X"03", X"e0", X"00", X"08",
X"35", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"35", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"9b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"bb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"db", X"00", X"00", X"03", X"e0", X"00", X"08",
X"36", X"fb", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"1b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"3b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"5b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"7b", X"00", X"00", X"03", X"e0", X"00", X"08",
X"37", X"9a", X"00", X"00", X"03", X"e0", X"00", X"08",
X"8f", X"bb", X"ff", X"f0", X"03", X"e0", X"00", X"08",
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X"03", X"e0", X"00", X"08", X"00", X"00", X"10", X"21",
X"00", X"80", X"10", X"21", X"3c", X"05", X"20", X"00",
X"8c", X"a3", X"00", X"04", X"00", X"00", X"00", X"00",
X"30", X"63", X"00", X"02", X"10", X"60", X"ff", X"fc",
X"3c", X"03", X"20", X"00", X"ac", X"62", X"00", X"00",
X"03", X"e0", X"00", X"08", X"00", X"00", X"00", X"00",
X"3c", X"03", X"20", X"00", X"8c", X"62", X"00", X"04",
X"00", X"00", X"00", X"00", X"30", X"42", X"00", X"01",
X"10", X"40", X"ff", X"fc", X"3c", X"02", X"20", X"00",
X"8c", X"42", X"00", X"00", X"03", X"e0", X"00", X"08",
X"00", X"02", X"16", X"02", X"63", X"6f", X"6d", X"70",
X"69", X"6c", X"65", X"20", X"74", X"69", X"6d", X"65",
X"3a", X"20", X"4a", X"75", X"6e", X"20", X"20", X"39",
X"20", X"32", X"30", X"31", X"32", X"20", X"2d", X"2d",
X"20", X"31", X"36", X"3a", X"33", X"38", X"3a", X"30",
X"32", X"0a", X"00", X"00", X"67", X"63", X"63", X"20",
X"76", X"65", X"72", X"73", X"69", X"6f", X"6e", X"3a",
X"20", X"20", X"34", X"2e", X"35", X"2e", X"32", X"0a",
X"00", X"00", X"00", X"00", X"0a", X"0a", X"48", X"65",
X"6c", X"6c", X"6f", X"20", X"57", X"6f", X"72", X"6c",
X"64", X"21", X"0a", X"0a", X"0a", X"00", X"00", X"00",
X"28", X"6e", X"75", X"6c", X"6c", X"29", X"00"
);
 
 
end package obj_code_pkg;
/trunk/vhdl/SoC/uart.vhdl
0,0 → 1,569
--##############################################################################
-- uart.vhdl -- Basic, hardwired RS232 UART.
--
-- Most operational parameters are hardcoded: 8 bit words, no parity, 1 stop
-- bit. The only parameter that can be configured in run time is the baud rate.
--
-- The receiver logic is a simplified copy of the 8051 UART. The bit period is
-- split in 16 sampling periods, and 3 samples are taken at the center of each
-- bit period. The bit value is decided by majority. The receiver logic has some
-- error recovery capability that should make this core reliable enough for
-- actual application use -- yet, the core does not have a format test bench.
--
-- See usage notes below.
--
--------------------------------------------------------------------------------
-- This file is free software (See COPYING.TXT)
--##############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
--------------------------------------------------------------------------------
-- UART programmer model
--------------------------------------------------------------------------------
--
-- The UART has a number of configuration registers addressable with input
-- signal addr_*_i:
--
-- [00] => Data buffer, both transmission and reception.
-- [01] => Status/control register (r/w).
-- [10] => Bit period register, low byte.
-- [11] => Bit period register, high byte.
--
--
-- Data buffers:
----------------
--
-- The same address [00b] is used for both the receive buffer and the
-- transmision buffer.
--
-- Writing to the data buffer when flag TxRdy is high will trigger a
-- transmission and clear flag TxRdy.
-- Writing to the data buffer when flag TxRdy is clear will have no effect.
--
-- Reading the data register when flag RxRdy is high will return the last
-- received data byte, and will clear flag RxRdy but NOT RxIrq.
-- Reading the register when flag RxRdy is clear will return indeterminate data,
-- which in practice will usually be the last byte received.
--
-- Interrupts:
--------------
--
-- The core has two interrupt sources tied to a single external irq line. The
-- sources are these:
--
-- -# Receiver interrupt: Raised when the stop bit is sampled and determined
-- to be valid (about the middle of the bit period).
-- If the stop bit is not valid (not high) then the interrupt is not
-- triggered. If a start bit is determined to be spurious (i.e. the falling
-- edge is detected but the bit value when sampled is not 0) then the
-- interrupt is not triggered.
-- This interrupt sets flag RxIrw in the status register.
-- -# Transmitter interrupt: Raised at the end of the transmission of the stop
-- bit.
-- This interrupt sets flag TxIrq in the status register 1 clock cycle after
-- the interrupt is raised.
--
-- The core does not have any interrupt enable mask. If any interrupt source
-- triggers, the output irq_o is asserted for one cycle. This is all the extent
-- of the interrupt processing done by this module.
--
-- Error detection:
-------------------
--
-- The core is capable of detecting and recovering from these error conditions:
--
-- -# When a start bit is determined to be spurious (i.e. the falling edge is
-- detected but the bit value when sampled is not 0) then the core returns to
-- its idle state (waiting for a new start bit).
-- -# If a stop bit is determined to be invalid (not 1 when sampled), the
-- reception interrupt is not triggered and the received byte is discarded.
-- -# When the 3 samples taken from the center of a bit period are not equal,
-- the bit value is decided by majority.
--
-- In none of the 3 cases does the core raise any error flag. It would be very
-- easy to include those flags in the core, but it would take a lot more time
-- to test them minimally and that's why they haven't been included.
--
-- Status register flags:
-------------------------
--
-- 7 6 5 4 3 2 1 0
-- +-------+-------+-------+-------+-------+-------+-------+-------+
-- | 0 | 0 | RxIrq | TxIrq | 0 | 0 | RxRdy | TxRdy |
-- +-------+-------+-------+-------+-------+-------+-------+-------+
-- h h W1C W1C h h r r
--
-- Bits marked 'h' are hardwired and can't be modified.
-- Bits marked 'r' are read only; they are set and clear by the UART core.
-- Bits marked W1C ('Write 1 Clear') are set by the UART core when an interrupt
-- has been triggered and must be cleared by the software by writing a '1'.
--
-- -# Status bit TxRdy is high when there isn't any transmission in progress.
-- It is cleared when data is written to the transmission buffer and is
-- raised at the same time the transmission interrupt is triggered.
-- -# Status bit RxRdy is raised at the same time the receive interrupt is
-- triggered and is cleared when the data register is read.
-- -# Status bit TxIrq is raised when the transmission interrupt is triggered
-- and is cleared when a 1 is written to it.
-- -# Status bit RxIrq is raised when the reception interrupt is triggered
-- and is cleared when a 1 is written to it.
--
-- When writing to the status/control registers, only flags TxIrq and RxIrq are
-- affected, and only when writing a '1' as explained above. All other flags
-- are read-only.
--
-- Baud rate configuration:
---------------------------
--
-- The baud rate is determined by the value of 14-bit register 'bit_period_reg'.
-- This register holds the length of the bit period in clock cycles and its
-- value may be hardcoded or configured at run time.
--
-- When generic HARDWIRED is true, bit_period_reg is hardwired with a value
-- computed from the value of generic BAUD_RATE. The bit period computation
-- needs to know the master clock rate, which should be given in generic
-- CLOCK_RATE.
-- Writes to the baud registers when HARDWIRED is true will be ignored.
--
-- When generic HARDWIRED is false, generics BAUD_RATE and CLOCK_RATE determine
-- the reset value of bit_period_reg, but the register can be changed at run
-- time by writing at addresses [10b] and [11b], which access the low and high
-- bytes of the register, respectively.
-- Reading from those register addresses returns the value of the status
-- register (a LUT saving measure) so the registers are effectively write-only.
--
--------------------------------------------------------------------------------
-- Core interface signals:
--
-- clk_i: Clock input, active rising edge.
-- reset_i: Synchronous reset.
-- txd_o: TxD UART output.
-- rxd_i: RxD UART input -- synchronization logic included.
-- irq_o: Interrupt output, asserted for 1 cycle when triggered.
-- data_i: Data bus, input.
-- data_o: Data bus, output.
-- addr_rd_i: Register selection address, read access (see above).
-- addr_wr_i: Register selection address, write access (see above).
-- wr_i: Write enable input.
-- rd_i: Read enable input.
-- ce_i: Chip enable, must be active at the same time as wr_i or rd_i.
--
--
-- No detailed explanation of the i/f timing can be given for lack of time.
-- The core reads and writes like a synchronous memory.
--------------------------------------------------------------------------------
 
entity uart is
generic (
HARDWIRED : boolean := true; -- Baud rate hardwired to constant value
BAUD_RATE : integer := 19200; -- Default (or hardwired) baud rate
CLOCK_FREQ : integer := 50E6); -- Clock rate
port (
rxd_i : in std_logic;
txd_o : out std_logic;
irq_o : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
addr_rd_i : in std_logic_vector(1 downto 0);
addr_wr_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
ce_i : in std_logic;
clk_i : in std_logic;
reset_i : in std_logic);
end uart;
 
architecture hardwired of uart is
 
-- Bit period expressed in master clock cycles
constant DEFAULT_BIT_PERIOD : integer := (CLOCK_FREQ / BAUD_RATE);
 
-- Bit sampling period is 1/16 of the baud rate.
constant DEFAULT_SAMPLING_PERIOD : integer := DEFAULT_BIT_PERIOD / 16;
 
 
 
--##############################################################################
 
-- Common signals
 
signal reset : std_logic;
signal clk : std_logic;
 
 
signal bit_period_reg : unsigned(13 downto 0);
signal sampling_period : unsigned(9 downto 0);
 
 
-- Interrupt & status register signals
 
signal tx_irq_flag : std_logic;
signal rx_irq_flag : std_logic;
signal load_stat_reg : std_logic;
signal load_tx_reg : std_logic;
 
-- Receiver signals
signal rxd_q : std_logic;
signal tick_ctr : unsigned(3 downto 0);
signal state : unsigned(3 downto 0);
signal next_state : unsigned(3 downto 0);
signal start_bit_detected : std_logic;
signal reset_tick_ctr : std_logic;
signal stop_bit_sampled : std_logic;
signal load_rx_buffer : std_logic;
signal stop_error : std_logic;
signal samples : std_logic_vector(2 downto 0);
signal sampled_bit : std_logic;
signal do_shift : std_logic;
signal rx_buffer : std_logic_vector(7 downto 0);
signal rx_shift_reg : std_logic_vector(9 downto 0);
signal tick_ctr_enable : std_logic;
signal tick_baud_ctr : unsigned(10 downto 0);
 
signal rx_rdy_flag : std_logic;
signal rx_irq : std_logic;
signal set_rx_rdy_flag : std_logic;
signal rxd : std_logic;
 
signal read_rx : std_logic;
signal status : std_logic_vector(7 downto 0);
 
-- Transmitter signals
 
signal tx_counter : unsigned(13 downto 0);
signal tx_data : std_logic_vector(10 downto 0);
signal tx_ctr_bit : unsigned(3 downto 0);
signal tx_busy : std_logic;
signal tx_irq : std_logic;
 
 
 
begin
 
-- Rename the most commonly used inputs to get rid of the i/o suffix
clk <= clk_i;
reset <= reset_i;
rxd <= rxd_i;
 
 
-- Serial port status byte -- only 2 status flags
status <=
"00" & rx_irq_flag & tx_irq_flag & -- Interrupt flags
"00" & rx_rdy_flag & (not tx_busy); -- State flags
 
-- Read register multiplexor
with addr_rd_i select data_o <=
rx_buffer when "00",
status when others;
 
 
load_tx_reg <= '1' when wr_i = '1' and ce_i = '1' and addr_wr_i = "00" else '0';
load_stat_reg <= '1' when wr_i = '1' and ce_i = '1' and addr_wr_i = "01" else '0';
read_rx <= '1' when rd_i = '1' and ce_i = '1' else '0';
 
rx_irq <= set_rx_rdy_flag;
irq_o <= rx_irq or tx_irq;
 
interrupt_flags:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
rx_irq_flag <= '0';
tx_irq_flag <= '0';
else
if set_rx_rdy_flag='1' then
rx_irq_flag <= '1';
elsif load_stat_reg='1' and data_i(5)='1' then
rx_irq_flag <= '0';
end if;
if tx_irq='1' then
tx_irq_flag <= '1';
elsif load_stat_reg='1' and data_i(4)='1' then
tx_irq_flag <= '0';
end if;
end if;
end if;
end process interrupt_flags;
 
 
baud_rate_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
bit_period_reg <= to_unsigned(DEFAULT_BIT_PERIOD,14);
else
if wr_i = '1' and ce_i = '1' then
if addr_wr_i = "10" then
bit_period_reg(7 downto 0) <= unsigned(data_i);
elsif addr_wr_i = "11" then
bit_period_reg(13 downto 8) <= unsigned(data_i(5 downto 0));
end if;
end if;
end if;
end if;
end process baud_rate_registers;
 
sampling_period <= bit_period_reg(13 downto 4);
-- Receiver --------------------------------------------------------------------
 
baud_counter:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tick_baud_ctr <= (others => '0');
else
if tick_baud_ctr=sampling_period then
tick_baud_ctr <= (others => '0');
else
tick_baud_ctr <= tick_baud_ctr + 1;
end if;
end if;
end if;
end process baud_counter;
 
tick_ctr_enable<= '1' when tick_baud_ctr=sampling_period else '0';
 
-- Register RxD at the bit sampling rate -- 16 times the baud rate.
rxd_input_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rxd_q <= '0';
else
if tick_ctr_enable='1' then
rxd_q <= rxd;
end if;
end if;
end if;
end process rxd_input_register;
 
-- We detect the start bit when...
start_bit_detected <= '1' when
state="0000" and -- ...we're waiting for the start bit...
rxd_q='1' and rxd='0' -- ...and we see RxD going 1-to-0
else '0';
 
-- As soon as we detect the start bit we synchronize the bit sampler to
-- the start bit's falling edge.
reset_tick_ctr <= '1' when start_bit_detected='1' else '0';
 
-- We have seen the end of the stop bit when...
stop_bit_sampled <= '1' when
state="1010" and -- ...we're in the stop bit period...
tick_ctr="1011" -- ...and we get the 11th sample in the bit period
else '0';
 
-- Load the RX buffer with the shift register when...
load_rx_buffer <= '1' when
stop_bit_sampled='1' and -- ...we've just seen the end of the stop bit...
sampled_bit='1' -- ...and its value is correct (1)
else '0';
 
-- Conversely, we detect a stop bit error when...
stop_error <= '1' when
stop_bit_sampled='1' and -- ...we've just seen the end of the stop bit...
sampled_bit='0' -- ...and its value is incorrect (0)
else '0';
 
-- tick_ctr is a counter 16 times faster than the baud rate that is aligned to
-- the falling edge of the start bit, so that when tick_ctr=0 we're close to
-- the start of a bit period.
bit_sample_counter:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tick_ctr <= "0000";
else
if tick_ctr_enable='1' then
-- Restart counter when it reaches 15 OR when the falling edge
-- of the start bit is detected; this is how we synchronize to the
-- start bit.
if tick_ctr="1111" or reset_tick_ctr='1' then
tick_ctr <= "0000";
else
tick_ctr <= tick_ctr + 1;
end if;
end if;
end if;
end if;
end process bit_sample_counter;
 
-- Main RX state machine:
-- 0 -> waiting for start bit
-- 1 -> sampling start bit
-- 2..9 -> sampling data bit 0 to 7
-- 10 -> sampling stop bit
next_state <=
-- Start sampling the start bit when we detect the falling edge
"0001" when state="0000" and start_bit_detected='1' else
-- Return to idle state if the start bit is not a clean 0
"0000" when state="0001" and tick_ctr="1010" and sampled_bit='1' else
-- Return to idle state at the end of the stop bit period
"0000" when state="1010" and tick_ctr="1111" else
-- Otherwise, proceed to next bit period at the end of each period
state + 1 when tick_ctr="1111" and do_shift='1' else
state;
rx_state_machine_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
state <= "0000";
else
if tick_ctr_enable='1' then
state <= next_state;
end if;
end if;
end if;
end process rx_state_machine_register;
 
-- Collect 3 RxD samples from the 3 central sampling periods of the bit period.
rx_sampler:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
samples <= "000";
else
if tick_ctr_enable='1' then
if tick_ctr="0111" then
samples(0) <= rxd;
end if;
if tick_ctr="1000" then
samples(1) <= rxd;
end if;
if tick_ctr="1001" then
samples(2) <= rxd;
end if;
end if;
end if;
end if;
end process rx_sampler;
 
-- Decide the value of the RxD bit by majority
with samples select
sampled_bit <= '0' when "000",
'0' when "001",
'0' when "010",
'1' when "011",
'0' when "100",
'1' when "101",
'1' when "110",
'1' when others;
 
rx_buffer_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_buffer <= "00000000";
set_rx_rdy_flag <= '0';
else
if tick_ctr_enable='1' and load_rx_buffer='1' and rx_rdy_flag='0' then
rx_buffer <= rx_shift_reg(8 downto 1);
set_rx_rdy_flag <= '1';
else
set_rx_rdy_flag <= '0';
end if;
end if;
end if;
end process rx_buffer_register;
 
rx_flag:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_rdy_flag <= '0';
else
if set_rx_rdy_flag='1' then
rx_rdy_flag <= '1';
else
if read_rx = '1' then
rx_rdy_flag <= '0';
end if;
end if;
end if;
end if;
end process rx_flag;
 
-- RX shifter control: shift in any state other than idle state (0)
do_shift <= state(0) or state(1) or state(2) or state(3);
 
rx_shift_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_shift_reg <= "1111111111";
else
if tick_ctr_enable='1' then
if tick_ctr="1010" and do_shift='1' then
rx_shift_reg(9) <= sampled_bit;
rx_shift_reg(8 downto 0) <= rx_shift_reg(9 downto 1);
end if;
end if;
end if;
end if;
end process rx_shift_register;
 
-- Transmitter -----------------------------------------------------------------
 
 
main_tx_process:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tx_data <= "10111111111";
tx_busy <= '0';
tx_irq <= '0';
tx_ctr_bit <= "0000";
tx_counter <= (others => '0');
elsif load_tx_reg='1' and tx_busy='0' then
tx_data <= "1"&data_i&"01";
tx_busy <= '1';
else
if tx_busy='1' then
if tx_counter = bit_period_reg then
tx_counter <= (others => '0');
tx_data(9 downto 0) <= tx_data(10 downto 1);
tx_data(10) <= '1';
if tx_ctr_bit = "1010" then
tx_busy <= '0';
tx_irq <= '1';
tx_ctr_bit <= "0000";
else
tx_ctr_bit <= tx_ctr_bit + 1;
end if;
else
tx_counter <= tx_counter + 1;
end if;
else
tx_irq <= '0';
end if;
end if;
end if;
end process main_tx_process;
 
txd_o <= tx_data(0);
 
end hardwired;
/trunk/vhdl/SoC/mips_soc.vhdl
0,0 → 1,293
--------------------------------------------------------------------------------
-- Synthesizable ION SoC -- CPU + cache + bootstrap ROM (BRAM) + UART
--------------------------------------------------------------------------------
--
--
--
--------------------------------------------------------------------------------
-- Generics
------------
--
--
--
--------------------------------------------------------------------------------
-- Memory map
--------------
--
--------------------------------------------------------------------------------
-- Copyright (C) 2012 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mips_pkg.all;
 
entity mips_soc is
generic (
CLOCK_FREQ : integer := 50000000;
BAUD_RATE : integer := 19200;
BOOT_BRAM_SIZE : integer := 1024;
OBJ_CODE : t_obj_code := default_object_code;
SRAM_ADDR_SIZE : integer := 17 -- < 10 to disable SRAM I/F
);
port(
clk : in std_logic;
reset : in std_logic;
interrupt : in std_logic_vector(7 downto 0);
-- interface to FPGA i/o devices
io_rd_data : in std_logic_vector(31 downto 0);
io_rd_addr : out std_logic_vector(31 downto 2);
io_wr_addr : out std_logic_vector(31 downto 2);
io_wr_data : out std_logic_vector(31 downto 0);
io_rd_vma : out std_logic;
io_byte_we : out std_logic_vector(3 downto 0);
-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
sram_data_wr : out std_logic_vector(15 downto 0);
sram_data_rd : in std_logic_vector(15 downto 0);
sram_byte_we_n : out std_logic_vector(1 downto 0);
sram_oe_n : out std_logic;
 
-- UART
uart_rxd : in std_logic;
uart_txd : out std_logic;
-- Debug info register output
debug_info : out t_debug_info
);
end; --entity mips_soc
 
architecture rtl of mips_soc is
 
-- Interface cpu-cache
signal cpu_data_addr : t_word;
signal cpu_data_rd_vma : std_logic;
signal cpu_data_rd : t_word;
signal cpu_code_rd_addr : t_pc;
signal cpu_code_rd : t_word;
signal cpu_code_rd_vma : std_logic;
signal cpu_data_wr : t_word;
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_mem_wait : std_logic;
signal cpu_ic_invalidate : std_logic;
signal cpu_cache_enable : std_logic;
signal unmapped_access : std_logic;
 
-- Interface to i/o
signal mpu_io_rd_data : std_logic_vector(31 downto 0);
signal mpu_io_wr_data : std_logic_vector(31 downto 0);
signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
signal mpu_io_rd_vma : std_logic;
signal mpu_io_byte_we : std_logic_vector(3 downto 0);
 
-- Interface to UARTs
signal uart_ce : std_logic;
signal uart_irq : std_logic;
signal uart_rd_byte : std_logic_vector(7 downto 0);
 
-- Bootstrap code BRAM
constant BOOT_BRAM_ADDR_SIZE : integer := log2(BOOT_BRAM_SIZE);
subtype t_boot_bram_address is std_logic_vector(BOOT_BRAM_ADDR_SIZE-1 downto 0);
-- Boot BRAM, initialized with constant object code table
signal boot_bram : t_word_table(0 to BOOT_BRAM_SIZE-1) :=
objcode_to_wtable(OBJ_CODE, BOOT_BRAM_SIZE);
 
-- NOTE: 'write' signals are a remnant from a previous version, to be removed
signal bram_rd_addr : t_boot_bram_address;
signal bram_wr_addr : t_boot_bram_address;
signal bram_rd_data : t_word;
signal bram_wr_data : t_word;
signal bram_byte_we : std_logic_vector(3 downto 0);
--------------------------------------------------------------------------------
begin
 
cpu: entity work.mips_cpu
port map (
interrupt => interrupt,
data_addr => cpu_data_addr,
data_rd_vma => cpu_data_rd_vma,
data_rd => cpu_data_rd,
code_rd_addr=> cpu_code_rd_addr,
code_rd => cpu_code_rd,
code_rd_vma => cpu_code_rd_vma,
data_wr => cpu_data_wr,
byte_we => cpu_byte_we,
mem_wait => cpu_mem_wait,
cache_enable=> cpu_cache_enable,
ic_invalidate=>cpu_ic_invalidate,
clk => clk,
reset => reset
);
 
cache: entity work.mips_cache
generic map (
BRAM_ADDR_SIZE => BOOT_BRAM_ADDR_SIZE,
SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
)
port map (
clk => clk,
reset => reset,
-- Interface to CPU core
data_addr => cpu_data_addr,
data_rd => cpu_data_rd,
data_rd_vma => cpu_data_rd_vma,
code_rd_addr => cpu_code_rd_addr,
code_rd => cpu_code_rd,
code_rd_vma => cpu_code_rd_vma,
byte_we => cpu_byte_we,
data_wr => cpu_data_wr,
mem_wait => cpu_mem_wait,
cache_enable => cpu_cache_enable,
ic_invalidate => cpu_ic_invalidate,
unmapped => unmapped_access,
-- interface to FPGA i/o devices
io_rd_data => mpu_io_rd_data,
io_wr_data => mpu_io_wr_data,
io_rd_addr => mpu_io_rd_addr,
io_wr_addr => mpu_io_wr_addr,
io_rd_vma => mpu_io_rd_vma,
io_byte_we => mpu_io_byte_we,
-- interface to synchronous 32-bit-wide FPGA BRAM
bram_rd_data => bram_rd_data,
bram_wr_data => bram_wr_data,
bram_rd_addr => bram_rd_addr,
bram_wr_addr => bram_wr_addr,
bram_byte_we => bram_byte_we,
-- interface to asynchronous 16-bit-wide external SRAM
sram_address => sram_address,
sram_data_rd => sram_data_rd,
sram_data_wr => sram_data_wr,
sram_byte_we_n => sram_byte_we_n,
sram_oe_n => sram_oe_n
);
 
 
--------------------------------------------------------------------------------
-- BRAM interface -- read only
 
fpga_ram_block:
process(clk)
begin
if clk'event and clk='1' then
bram_rd_data <= boot_bram(conv_integer(unsigned(bram_rd_addr)));
end if;
end process fpga_ram_block;
 
 
--------------------------------------------------------------------------------
-- Debug stuff
 
-- Register some debug signals. These are meant to be connected to LEDs on a
-- dev board, or maybe to logic analyzer probes. They are not useful once
-- the core is fully debugged.
debug_info_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
debug_info.unmapped_access <= '0';
else
if unmapped_access='1' then
-- This flag will be asserted permanently after any kind of
-- unmapped access (code, data read or data write).
debug_info.unmapped_access <= '1';
end if;
end if;
-- This flag will be asserted as long as the cache is enabled
debug_info.cache_enabled <= cpu_cache_enable;
end if;
end process debug_info_register;
 
 
--------------------------------------------------------------------------------
-- UART -- 8-bit interface, connected to LOW byte of word (address *3h)
 
uart : entity work.uart
generic map (
BAUD_RATE => BAUD_RATE,
CLOCK_FREQ => CLOCK_FREQ
)
port map (
clk_i => clk,
reset_i => reset,
irq_o => uart_irq,
data_i => mpu_io_wr_data(7 downto 0),
data_o => uart_rd_byte,
addr_rd_i => mpu_io_rd_addr(3 downto 2),
addr_wr_i => mpu_io_wr_addr(3 downto 2),
ce_i => uart_ce,
wr_i => mpu_io_byte_we(3),
rd_i => mpu_io_rd_vma,
rxd_i => uart_rxd,
txd_o => uart_txd
);
-- UART chip enable
uart_ce <= '1'
when (mpu_io_rd_vma='1' or mpu_io_byte_we(3)='1') and
mpu_io_rd_addr(31 downto 28)=X"2" and
mpu_io_rd_addr(15 downto 12)=X"0"
else '0';
 
--------------------------------------------------------------------------------
-- I/O port multiplexor
-- IO Rd mux: either the UART data/status word od the IO coming from outside
mpu_io_rd_data <=
X"000000" & uart_rd_byte when uart_ce = '1' else
io_rd_data;
 
-- io_rd_data
io_rd_addr <= mpu_io_rd_addr;
io_wr_addr <= mpu_io_wr_addr;
io_wr_data <= mpu_io_wr_data;
io_rd_vma <= mpu_io_rd_vma;
io_byte_we <= mpu_io_byte_we;
 
 
end architecture rtl;

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