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  • This comparison shows the changes necessary to convert path 
    /ion
    from Rev 223 to Rev 224
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Rev 223 → Rev 224

/trunk/vhdl/SoC/mips_soc.vhdl
1,7 → 1,61
--------------------------------------------------------------------------------
-- Synthesizable MPU -- CPU + cache + bootstrap ROM (BRAM) + UART
-- Synthesizable ION SoC -- CPU + cache + bootstrap ROM (BRAM) + UART
--------------------------------------------------------------------------------
-- Copyright (C) 2011 Jose A. Ruiz
-- This SoC is meant as a vehicle for building demos around the ION CPU, and not
-- really as an useable SoC.
--------------------------------------------------------------------------------
--
-- This SoC includes a small BRAM block mapped at 0xbfc00000 and used to hold
-- the application's bootstrap code.
-- The bootstrap object code is passed as a generic in the form of a byte array
-- (type t_obj_code, defined in mips_pkg). This byte array can be generated with
-- script 'build_pkg.py', included in the tools directory.
-- In the present implementation, the boot BRAM can't be omitted even if the
-- memory map is changed or its size is set to zero.
--
--------------------------------------------------------------------------------
-- Generics
------------
--
-- BOOT_BRAM_SIZE: Size of boot BRAM in 32-bit words. Can't be zero.
-- OBJ_CODE: Bootstrap object code (mapped at 0xbfc00000).
-- SRAM_ADDR_SIZE: Size of address bus for SRAM interface.
-- CLOCK_FREQ: Clock rate in Hz. Used for the UART configuration.
-- BAUD_RATE: UART baud rate.
--
--------------------------------------------------------------------------------
-- Memory map
--------------
--
-- The memory map used in this SoC is defined in package mips_pkg, in function
-- decode_addr_mips1. It is used in the module 'mips_cache.vhdl', where
-- the I- and D-Caches are implemented along with the memory controller -- see
-- the project doc.
-- This map has been chosen for development convenience and includes all the
-- external memory types available in the development target, Terasic's DE-1
-- board. It is meant to change as development progresses.
--
-- A[31..27]
-- 00000 => Static, 16-bit (SRAM)
-- 10000 => Static, 16-bit (SRAM)
-- 00100 => I/O
-- 10110 => Static, 8-bit (flash)
-- 10111 => Internal BRAM (boot BRAM)
--
-- I/O devices
---------------
--
-- The only I/O device in this SoC is an UART (module 'uart.vhdl':
--
-- 2XXX0XXX0h => UART register 0
-- 2XXX0XXX4h => UART register 1
-- 2XXX0XXX8h => UART register 2
-- 2XXX0XXXch => UART register 3
--
-- The UART is hardwired to a fixed baud rate and can be configured through
-- generics.
--------------------------------------------------------------------------------
-- Copyright (C) 2012 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
30,12 → 84,16
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mips_pkg.all;
use work.code_rom_pkg.all;
 
entity mips_mpu is
entity mips_soc is
generic (
CLOCK_FREQ : integer := 50000000;
SRAM_ADDR_SIZE : integer := 17
CLOCK_FREQ : integer := 50000000;
BAUD_RATE : integer := 19200;
BOOT_BRAM_SIZE : integer := 1024;
-- FIXME Boot BRAM can't be omitted
OBJ_CODE : t_obj_code := default_object_code;
SRAM_ADDR_SIZE : integer := 17 -- < 10 to disable SRAM I/F
-- FIXME SRAM I/F can't be disabled
);
port(
clk : in std_logic;
51,7 → 109,7
io_byte_we : out std_logic_vector(3 downto 0);
-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
sram_address : out std_logic_vector(SRAM_ADDR_SIZE-1 downto 0);
sram_data_wr : out std_logic_vector(15 downto 0);
sram_data_rd : in std_logic_vector(15 downto 0);
sram_byte_we_n : out std_logic_vector(1 downto 0);
61,14 → 119,14
uart_rxd : in std_logic;
uart_txd : out std_logic;
-- Debug info
-- Debug info register output
debug_info : out t_debug_info
);
end; --entity mips_mpu
end; --entity mips_soc
 
architecture rtl of mips_mpu is
architecture rtl of mips_soc is
 
-- interface cpu-cache
-- Interface cpu-cache
signal cpu_data_addr : t_word;
signal cpu_data_rd_vma : std_logic;
signal cpu_data_rd : t_word;
82,8 → 140,7
signal cpu_cache_enable : std_logic;
signal unmapped_access : std_logic;
 
 
-- interface to i/o
-- Interface to i/o
signal mpu_io_rd_data : std_logic_vector(31 downto 0);
signal mpu_io_wr_data : std_logic_vector(31 downto 0);
signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
91,24 → 148,26
signal mpu_io_rd_vma : std_logic;
signal mpu_io_byte_we : std_logic_vector(3 downto 0);
 
-- interface to UARTs
signal uart_rd_word : t_word;
signal uart_tx_rdy : std_logic := '1';
signal uart_rx_rdy : std_logic := '1';
signal uart_write : std_logic;
signal uart_read : std_logic;
signal uart_read_rx : std_logic;
signal uart_data_rx : std_logic_vector(7 downto 0);
-- Interface to UARTs
signal uart_ce : std_logic;
signal uart_irq : std_logic;
signal uart_rd_byte : std_logic_vector(7 downto 0);
 
-- interface to bootstrap code BRAM
-- Bootstrap code BRAM
constant BOOT_BRAM_ADDR_SIZE : integer := log2(BOOT_BRAM_SIZE);
subtype t_boot_bram_address is std_logic_vector(BOOT_BRAM_ADDR_SIZE-1 downto 0);
-- Boot BRAM, initialized with constant object code table
signal boot_bram : t_word_table(0 to BOOT_BRAM_SIZE-1) :=
objcode_to_wtable(OBJ_CODE, BOOT_BRAM_SIZE);
 
-- NOTE: 'write' signals are a remnant from a previous version, to be removed
signal bram_rd_addr : t_bram_address;
signal bram_wr_addr : t_bram_address;
signal bram_rd_addr : t_boot_bram_address;
signal bram_wr_addr : t_boot_bram_address;
signal bram_rd_data : t_word;
signal bram_wr_data : t_word;
signal bram_byte_we : std_logic_vector(3 downto 0);
 
 
--------------------------------------------------------------------------------
begin
 
137,7 → 196,7
 
cache: entity work.mips_cache
generic map (
BRAM_ADDR_SIZE => CODE_BRAM_ADDR_SIZE,
BRAM_ADDR_SIZE => BOOT_BRAM_ADDR_SIZE,
SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
)
port map (
186,13 → 245,13
 
 
--------------------------------------------------------------------------------
-- BRAM interface
-- BRAM interface -- read only
 
fpga_ram_block:
process(clk)
begin
if clk'event and clk='1' then
bram_rd_data <= code_bram(conv_integer(unsigned(bram_rd_addr)));
bram_rd_data <= boot_bram(conv_integer(unsigned(bram_rd_addr)));
end if;
end process fpga_ram_block;
 
216,7 → 275,7
debug_info.unmapped_access <= '1';
end if;
end if;
-- This flag will be asserted as long as the cache is enabled
debug_info.cache_enabled <= cpu_cache_enable;
end if;
end process debug_info_register;
223,62 → 282,45
 
 
--------------------------------------------------------------------------------
-- UART -- 8-bit interface, connected to LOW byte of word (address *3h)
 
serial_rx : entity work.rs232_rx
generic map (
CLOCK_FREQ => CLOCK_FREQ
uart : entity work.uart
generic map (
BAUD_RATE => BAUD_RATE,
CLOCK_FREQ => CLOCK_FREQ
)
port map(
rxd => uart_rxd,
data_rx => uart_data_rx,
rx_rdy => uart_rx_rdy,
read_rx => uart_read_rx,
clk => clk,
reset => reset
);
 
 
-- '1'-> Read some UART register (0x2---0---)
uart_read <= '1'
when mpu_io_rd_vma='1' and
mpu_io_rd_addr(31 downto 28)=X"2" and
mpu_io_rd_addr(15 downto 12)=X"0"
port map (
clk_i => clk,
reset_i => reset,
irq_o => uart_irq,
data_i => mpu_io_wr_data(7 downto 0),
data_o => uart_rd_byte,
addr_rd_i => mpu_io_rd_addr(3 downto 2),
addr_wr_i => mpu_io_wr_addr(3 downto 2),
ce_i => uart_ce,
wr_i => mpu_io_byte_we(3),
rd_i => mpu_io_rd_vma,
rxd_i => uart_rxd,
txd_o => uart_txd
);
-- UART chip enable
uart_ce <= '1'
when (mpu_io_rd_addr(15 downto 12)=X"0" or
mpu_io_wr_addr(15 downto 12)=X"0")
else '0';
 
-- '1'-> Read UART Rx data (0x2---0-0-)
-- (This signal clears the RX 1-char buffer)
uart_read_rx <= '1'
when uart_read='1' and
mpu_io_rd_addr( 7 downto 4)=X"0"
else '0';
 
-- '1'-> Write UART Tx register (trigger UART Tx) (0x20000000)
uart_write <= '1'
when mpu_io_byte_we/="0000" and
mpu_io_wr_addr(31 downto 28)=X"2" and
mpu_io_wr_addr(15 downto 12)=X"0"
else '0';
 
serial_tx : entity work.rs232_tx
generic map (
CLOCK_FREQ => CLOCK_FREQ
)
port map(
clk => clk,
reset => reset,
rdy => uart_tx_rdy,
load => uart_write,
data_i => mpu_io_wr_data(7 downto 0),
txd => uart_txd
);
 
-- Both UART rd addresses 000 and 020 read the same word (save a mux), but only
-- address 000 clears the rx buffer.
uart_rd_word <= uart_data_rx & X"00000" & "00" & uart_tx_rdy & uart_rx_rdy;
 
-- IO Rd mux: either the UART data/status word od the IO coming from outside
--------------------------------------------------------------------------------
-- I/O port multiplexor
-- IO Rd mux: either the UART data/status word or the IO coming from outside
mpu_io_rd_data <=
uart_rd_word when mpu_io_rd_addr(15 downto 12)=X"0" else
X"000000" & uart_rd_byte when mpu_io_rd_addr(19 downto 12)=X"00" else
io_rd_data;
 
-- io_rd_data

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