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URL https://opencores.org/ocsvn/ion/ion/trunk

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    /ion
    from Rev 228 to Rev 229
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Rev 228 → Rev 229

/trunk/src/hello/makefile
67,20 → 67,22
 
#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
 
#-- Create VHDL file for simulation test bench using TB2 template
#-- Create VHDL package with data and parameters for simulation
sim: hello demo
$(TO_VHDL) --code hello.code --data hello.data \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
--log_trigger=0xbfc00000 \
-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb2_template.vhdl \
-o $(TB_DIR)/mips_tb2.vhdl -e mips_tb2
$(TO_VHDL) --code hello.code --data hello.data \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
--log_trigger=0xbfc00000 \
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \
-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2
$(VHDL_OBJ_PKG) --project="Hello World" \
--package sim_params_pkg \
--bin hello.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
--bin hello.data --name sram_init --xram_size $(XRAM_SIZE)\
--name prom_init --flash_size 0 \
--output $(TB_DIR)/sim_params_pkg.vhdl \
-s $(SIM_LENGTH) --log_trigger=0xbfc00000 \
 
#-- Create VHDL file for simulation test bench using TB0 template
#-- This will instantiate the CPU without any caches or memory controller and
#-- will run the program off of an initialized ROM connected to the code
#-- interface.
#-- NOTE: This target has not been used in some time and may be broken. It's
#-- here because it can still be useful in an emergency.
sim_bram: hello
$(TO_VHDL) --code hello.code --data hello.data \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
87,12 → 89,12
-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb0_template.vhdl \
-o $(TB_DIR)/mips_tb2.vhdl -e mips_tb2
 
#-- Create VHDL file for hardware demo
#-- Create VHDL package with data and parameters for simulation and syntesis
demo: hello
$(TO_VHDL) --code hello.code --data hello.data \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-v $(SRC_DIR)/code_rom_template.vhdl -n "Hello World" \
-o $(DEMO_DIR)/code_rom_pkg.vhdl
$(VHDL_OBJ_PKG) --project="Hello World" \
--package obj_code_pkg \
--bin hello.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
--output $(DEMO_DIR)/../SoC/bootstrap_code_pkg.vhdl
 
 
#-- And now the usual housekeeping stuff ---------------------------------------
/trunk/src/common/libsoc/src/hw.h
13,8 → 13,8
 
#define UART_TX (0x20000000) /**< Addr of TX buffer */
#define UART_RX (0x20000000) /**< Addr of RX buffer */
#define UART_STATUS (0x20000020) /**< Addr of status register */
#define UART_RXRDY_MASK (0x00000001) /**< Flag mask for 'RX ready' */
#define UART_TXRDY_MASK (0x00000002) /**< Flag mask for 'TX ready' */
#define UART_STATUS (0x20000004) /**< Addr of status register */
#define UART_RXRDY_MASK (0x00000002) /**< Flag mask for 'RX ready' */
#define UART_TXRDY_MASK (0x00000001) /**< Flag mask for 'TX ready' */
 
#endif // HW_H_INCLUDED
/trunk/src/common/libsoc/src/hw_ion_mpu.c
27,12 → 27,12
/** Replacement for the standard C library getchar. */
int getchar(void){
uint32_t uart;
uint8_t c;
while(1){
uart = *((volatile uint32_t *)UART_STATUS);
if(uart & UART_RXRDY_MASK) break;
}
uart = *((volatile uint32_t *)UART_RX);
uart = (uart >> 24) & 0x0ff;
return (int)uart;
c = *((volatile uint8_t *)UART_RX);
return (int)c;
}
/trunk/src/common/makefile
40,7 → 40,6
LD = $(BIN_MIPS)/mips-sde-elf-ld
DUMP = $(BIN_MIPS)/mips-sde-elf-objdump
COPY = $(BIN_MIPS)/mips-sde-elf-objcopy
TO_VHDL = python ../bin2hdl.py
 
else
#**** Customize for Linux
54,15 → 53,19
LD = $(BIN_MIPS)/mips-unknown-linux-uclibc-ld
DUMP = $(BIN_MIPS)/mips-unknown-linux-uclibc-objdump
COPY = $(BIN_MIPS)/mips-unknown-linux-uclibc-objcopy
TO_VHDL = python ../bin2hdl.py
 
endif
 
### VHDL source file manipulation tools ########################################
ION_TOOLS = ../../tools
TO_VHDL = python $(ION_TOOLS)/bin2hdl/bin2hdl.py
VHDL_OBJ_PKG = python $(ION_TOOLS)/build_pkg/build_pkg.py -t $(ION_TOOLS)/build_pkg/templates
 
### Default system parameters -- to be replaced in application makefile ########
 
# 'CODE_BRAM' is meant to be a small BRAM (2 to 4KB) used for bootstrapping.
# 'DATA_BRAM' is a small BRAM connected to the data ports, used for debugging.
# 'XRAM' is meant to be the main external RAM, either SRAM or SDRAM.
# 'XRAM' is meant to be external SRAM
 
 
# Default location of code BRAM is on the reset vector address
73,7 → 76,7
DATA_BRAM_SIZE = 256
# Default address of BRAM -- used in some simulation-only tests, see makefiles
DATA_BRAM_ADDRESS = 0x10000
# Default size of data external RAM (XRAM) in 32-bit words (for simulation)
# Default size of data external SRAM (XRAM) in 16-bit words (for simulation)
XRAM_SIZE = 2048
# Default address of XRAM
XRAM_ADDRESS = 0x80000000
93,7 → 96,7
 
### Build options -- to be replaced in application makefile ####################
 
# Don't use gcc builtin functions, and try to target MIPS-I architecture
# Don't use gcc builtin functions, and try to target MIPS-I architecture.
# This will prevent usage of unimplemented opcodes but will insert nops after
# load instructions, which Ion does not need.
# (See comment above about -G0 flag)
/trunk/src/readme.txt
10,18 → 10,15
toolchains and have been occasionally tested with the Buildroot toolchain
for GNU/Linux.
 
Most makefiles have two targets, to create a simulation test bench and a
synthesizable demo.
Most makefiles have two targets, to create a package for the simulation test
bench or for the synthesizable demo.
 
Target 'sim' will build a the simulation test bench package as vhdl file
'/vhdl/tb/sim_params_pkg.vhdl'. This is the default test bench expected by the
simulation script '/sim/mips_tb.do'. The template used to build the package is
file '/src/sim_params_template.pkg' and the tool used to insert the data into
the template is the python script '/src/bin2hdl.py'.
'/vhdl/tb/sim_params_pkg.vhdl'. The tool used to build the package is the
python script '/tools/build_pkg/build_pkg.py'.
 
Target 'demo' will build a package for the synthesizable demo as file
'/vhdl/demo/code_rom_pkg.vhdl', from template file '/code_rom_template.vhdl',
using the same python script.
'/vhdl/SoC/bootstrap_code_pkg.vhdl', using the same python script.
 
The build process will produce a number of binary files that can be run on the
software simulator. A DOS BATCH file has been provided for each sample that
46,12 → 43,12
Building VHDL code from templates:
==================================
 
The python script 'bin2hdl.py' is used by all the samples to insert binary data
on vhdl templates.
The python script '/tools/build_pkg/build_pkg.py' is used by all the samples to
insert binary data on vhdl templates, building VHDL packages.
Assuming you have Python 2.5 or later in your machine, call the script with
 
python bin2hdl.py --help
python build_pkg.py --help
 
to get a short description and usage instructions.
There's a more detailed description in the project main doc (Well, I hope there
is one by the time you read this, documentation has been falling behind lately).
There's a more detailed description in script source.
 
/trunk/src/opcodes/makefile
7,7 → 7,7
# FPGA Block RAM parameters
BRAM_START = 0xbfc00000
CODE_BRAM_SIZE = 2048
CODE_BRAM_SIZE = 4096
# External RAM parameters (size in words)
XRAM_SIZE = 1024
XRAM_START = 0x00000000
28,18 → 28,16
$(COPY) -I elf32-big -O binary opcodes.axf opcodes.bin
$(COPY) -I elf32-big -j.data -j.bss -O binary opcodes.axf opcodes.data
 
# Create VHDL file for simulation test bench from TB2 template
#-- Create VHDL package with data and parameters for simulation
sim: opcodes
$(TO_VHDL) --code opcodes.bin --data opcodes.data --log_trigger=0xbfc00000 \
--code_size $(CODE_BRAM_SIZE) --data_size $(DATA_BRAM_SIZE) \
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \
-o $(TB_DIR)\\sim_params_pkg.vhdl -e dummy -n "Opcode tester"
$(TO_VHDL) --code opcodes.bin --data opcodes.data --log_trigger=0xbfc00000 \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-v $(SRC_DIR)/code_rom_template.vhdl -n "Opcode tester" \
-o $(DEMO_DIR)/code_rom_pkg.vhdl
$(VHDL_OBJ_PKG) --project="Opcode tester" \
--package sim_params_pkg \
--bin opcodes.bin --name obj_code --bram_size $(CODE_BRAM_SIZE) \
--bin opcodes.data --name sram_init --xram_size $(XRAM_SIZE) \
--name prom_init --flash_size 0 \
--output $(TB_DIR)/sim_params_pkg.vhdl \
-s $(SIM_LENGTH) --log_trigger=0xbfc00000 \
 
 
#-- And now the usual housekeeping stuff ---------------------------------------
 
/trunk/src/adventure/makefile
12,7 → 12,7
 
# FPGA Block RAM parameters
BRAM_START = 0xbfc00000
CODE_BRAM_SIZE = 2048
CODE_BRAM_SIZE = 512
# External RAM parameters (size in words)
XRAM_SIZE = 200000
XRAM_START = 0x00000000
102,26 → 102,23
 
 
 
# Create VHDL file for simulation test bench using TB2 template
#-- Create VHDL package with data and parameters for simulation
sim: bootstrap adventure demo
$(TO_VHDL) --code bootstrap.code --log_trigger=b0000000 \
--flash adventure.bin --flash_size $(FLASH_SIM_SIZE) \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \
-o $(TB_DIR)\\mips_tb2.vhdl -e dummy -n "Adventure"
$(TO_VHDL) --code bootstrap.code --log_trigger=b0000000 \
--flash adventure.bin --flash_size $(FLASH_SIM_SIZE) \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-s $(SIM_LENGTH) -v $(SRC_DIR)\\sim_params_template.vhdl \
-o $(TB_DIR)\\sim_params_pkg.vhdl -e dummy -n "Adventure"
$(VHDL_OBJ_PKG) --project="Adventure" \
--package sim_params_pkg \
--bin bootstrap.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
--name sram_init --xram_size $(XRAM_SIZE) \
--bin adventure.bin --name prom_init --flash_size $(FLASH_SIM_SIZE) \
--output $(TB_DIR)/sim_params_pkg.vhdl \
-s $(SIM_LENGTH) --log_trigger=0xb0000000 \
 
 
# Create VHDL file for hardware demo
demo: bootstrap adventure
$(TO_VHDL) --code bootstrap.code \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-v $(SRC_DIR)/code_rom_template.vhdl -n "Adventure" \
-o $(DEMO_DIR)/code_rom_pkg.vhdl
$(VHDL_OBJ_PKG) --project="Adventure" \
--package obj_code_pkg \
--bin bootstrap.code --name obj_code \
--output $(DEMO_DIR)/../SoC/bootstrap_code_pkg.vhdl
 
 
#-- And now the usual housekeeping stuff ---------------------------------------
/trunk/src/memtest/memtest.s
41,10 → 41,11
#---- UART stuff
.set UART_BASE, 0x20000000 # UART base address
.set UART_TX, 0x0000 # TX reg offset
.set UART_STATUS, 0x0020 # status reg offset
.set UART_STATUS, 0x0004 # status reg offset
.set UART_TX_RDY, 0x0001 # tx ready flag mask
 
#---- Debug register block -- 4 read-write, 32-bit registers
.set DEBUG_BASE, 0x2000f000 # Debug block base
.set DEBUG_BASE, 0x20010020 # Debug block base
#---------------------------------------------------------------------------
 
396,11 → 397,26
blt $a2,$a1,inv_i_cache_loop
addi $a2,1
 
# Now, the D-Cache is different. To invalidate a D-Cache line you just
# read from it (by proper selection of a dummy target address) while bits
# CP0[12].17:16=01. The data read is undefined and should be discarded.
 
li $a0,0 # Use any base address that is mapped
li $a2,0
li $a1,DCACHE_NUM_LINES-1
inv_d_cache_loop:
lw $zero,0($a0)
addi $a0,DCACHE_LINE_SIZE*4
blt $a2,$a1,inv_d_cache_loop
addi $a2,1
lui $a1,0x0002 # Leave with cache enabled
mfc0 $a0,$12
li $a1,0x00020000 # Leave cache enabled
or $a0,$a0,$a1
andi $a0,$a0,0xffff
or $a1,$a0,$a1
jr $ra
mtc0 $a0,$12
mtc0 $a1,$12
 
 
 
420,7 → 436,7
addiu $a0,1
puts_wait_tx_rdy:
lw $v1,UART_STATUS($a2)
andi $v1,$v1,0x02
andi $v1,$v1,UART_TX_RDY
beqz $v1,puts_wait_tx_rdy
nop
sw $v0,UART_TX($a2)
446,7 → 462,7
lb $v0,0($s2)
put_hex_wait_tx_rdy:
lw $v1,UART_STATUS($a2)
andi $v1,$v1,0x02
andi $v1,$v1,UART_TX_RDY
beqz $v1,put_hex_wait_tx_rdy
nop
sw $v0,UART_TX($a2)
/trunk/src/memtest/readme.txt
10,4 → 10,6
unprogrammed you will skip the final part of the test (execution from 8-bit
static memory).
 
 
Note that the very first test, "Testing D-Cache with back-to-back pairs of RD &
WR cycles" WILL fail in the hardware demo because it relies on debug registers
only present in the simulation test bench.
/trunk/src/memtest/makefile
4,12 → 4,16
# We'll run the simulation for long enough to complete the test
SIM_LENGTH = 400000
 
# FPGA Block RAM parameters
# FPGA Block RAM parameters (size in words)
BRAM_START = 0xbfc00000
CODE_BRAM_SIZE = 2048
# Simulated FLASH parameters (size in bytes)
FLASH_START = 0xb0000000
# External RAM parameters (size in words)
XRAM_SIZE = 1024
FLASH_SIZE = 4096
# External RAM parameters (size in 16-bit halfwords)
# This is the RAM size simulated by slite; set the same value so the execution
# logs match.
XRAM_SIZE = 2048
XRAM_START = 0x00000000
# Set to > 0 to initialize and enable the cache before running the tests
TEST_CACHE = 1
66,26 → 70,23
#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
# Create VHDL file for simulation test bench using TB2 template
#-- Create VHDL package with data and parameters for simulation
sim: memtest demo
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \
--flash flash.bin --flash_size 4096 \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \
-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \
--flash flash.bin --flash_size 4096 \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \
-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2
$(VHDL_OBJ_PKG) --project="Memtest" \
--package sim_params_pkg \
--bin memtest.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
--bin memtest.data --name sram_init --xram_size $(XRAM_SIZE) \
--bin flash.bin --name prom_init --flash_size $(FLASH_SIZE) \
--output $(TB_DIR)/sim_params_pkg.vhdl \
-s $(SIM_LENGTH) --log_trigger=0xbfc00000 \
 
 
# Create VHDL file for hardware demo
#-- Create VHDL package with data and parameters for syntesis
demo: memtest
$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xb0000000 \
--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
-v $(SRC_DIR)/code_rom_template.vhdl -n "Memory test" \
-o $(DEMO_DIR)/code_rom_pkg.vhdl
$(VHDL_OBJ_PKG) --project="Memtest" \
--package obj_code_pkg \
--bin memtest.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
--output $(DEMO_DIR)/../SoC/bootstrap_code_pkg.vhdl
 
#-- And now the usual housekeeping stuff ---------------------------------------
/trunk/src/memtest/flash.s
32,7 → 32,8
#---- UART stuff
.set UART_BASE, 0x20000000 # UART base address
.set UART_TX, 0x0000 # TX reg offset
.set UART_STATUS, 0x0020 # status reg offset
.set UART_STATUS, 0x0004 # status reg offset
.set UART_TX_RDY, 0x0001 # tx ready flag mask
 
#---------------------------------------------------------------------------
 
253,7 → 254,7
addiu $a0,1
puts_wait_tx_rdy:
lw $v1,UART_STATUS($a2)
andi $v1,$v1,0x02
andi $v1,$v1,UART_TX_RDY
beqz $v1,puts_wait_tx_rdy
nop
sw $v0,UART_TX($a2)
279,7 → 280,7
lb $v0,0($s2)
put_hex_wait_tx_rdy:
lw $v1,UART_STATUS($a2)
andi $v1,$v1,0x02
andi $v1,$v1,UART_TX_RDY
beqz $v1,put_hex_wait_tx_rdy
nop
sw $v0,UART_TX($a2)

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