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  • This comparison shows the changes necessary to convert path 
    /ion
    from Rev 63 to Rev 64
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  •

Rev 63 → Rev 64

/trunk/vhdl/mips_cache_stub.vhdl
230,12 → 230,16
-- 01 -> SRAM
-- 10 -> IO
-- 11 -> Unmapped
signal code_rd_area : std_logic_vector(1 downto 0);
signal data_rd_area : std_logic_vector(1 downto 0);
signal data_wr_area : std_logic_vector(1 downto 0);
 
signal code_rd_attr : t_range_attr;
signal data_rd_attr : t_range_attr;
signal data_wr_attr : t_range_attr;
signal code_rd_type : t_memory_type;
signal data_rd_type : t_memory_type;
signal data_wr_type : t_memory_type;
 
 
 
begin
 
--------------------------------------------------------------------------------
255,13 → 259,14
end if;
end process cache_state_machine_regs;
 
-- The code state machine occasionally 'waits' for the
-- (The code state machine occasionally 'waits' for the D-cache)
code_state_machine_transitions:
process(cps, dps, code_rd_vma, code_miss, code_rd_area,
process(cps, dps, code_rd_vma, code_miss, code_rd_type,
write_pending, read_pending)
begin
case cps is
when code_normal =>
-- FIXME wrong logic, these signals are not active in the same cycle
if code_rd_vma='1' and code_miss='1' and
read_pending='0' and write_pending='0' then
cns <= code_refill_bram_0; -- FIXME check memory area, SRAM!
307,24 → 312,24
-- This state machine does not overlap IO/BRAM/SRAM accesses for simplicity.
 
data_state_machine_transitions:
process(dps, write_pending, read_pending, data_rd_area, data_wr_area)
process(dps, write_pending, read_pending, data_rd_type, data_wr_type)
begin
case dps is
when data_normal =>
if write_pending='1' then
case data_wr_area is
when "00" => dns <= data_ignore_write; -- Write to BRAM ignored
when "01" => dns <= data_writethrough_sram_0;
when "10" => dns <= data_write_io_0;
when others => dns <= dps; -- Write to undecoded area ignored
case data_wr_type is
when MT_BRAM => dns <= data_ignore_write;
when MT_SRAM_16B => dns <= data_writethrough_sram_0;
when MT_IO_SYNC => dns <= data_write_io_0;
when others => dns <= dps; -- ignore write to undecoded area
end case;
elsif read_pending='1' then
case data_rd_area is
when "00" => dns <= data_refill_bram_0;
when "01" => dns <= data_refill_sram_0;
when "10" => dns <= data_read_io_0;
when others => dns <= dps; -- ignore read from undecoded area
case data_rd_type is
when MT_BRAM => dns <= data_refill_bram_0;
when MT_SRAM_16B => dns <= data_refill_sram_0;
when MT_IO_SYNC => dns <= data_read_io_0;
when others => dns <= dps; -- ignore read from undec. area
-- FIXME should raise debug flag
end case;
else
445,22 → 450,32
data_wr_addr_mask <= data_wr_addr_reg(31 downto t_addr_decode'low);
 
 
with code_rd_addr_mask select code_rd_area <=
"00" when ADDR_BOOT,
"01" when ADDR_XRAM,
"11" when others;
code_rd_attr <= decode_addr(code_rd_addr_mask);
code_rd_type <= code_rd_attr(6 downto 4);
 
with data_rd_addr_mask select data_rd_area <=
"00" when ADDR_BOOT,
"01" when ADDR_XRAM,
"10" when ADDR_IO,
"11" when others;
data_rd_attr <= decode_addr(data_rd_addr_mask);
data_rd_type <= data_rd_attr(6 downto 4);
 
with data_wr_addr_mask select data_wr_area <=
"01" when ADDR_XRAM,
"10" when ADDR_IO,
"11" when others;
data_wr_attr <= decode_addr(data_wr_addr_mask);
data_wr_type <= data_wr_attr(6 downto 4);
 
 
--with code_rd_addr_mask select code_rd_type <=
-- "000" when ADDR_BOOT,
-- "001" when ADDR_XRAM,
-- "011" when others;
--
--with data_rd_addr_mask select data_rd_type <=
-- "000" when ADDR_BOOT,
-- "001" when ADDR_XRAM,
-- "010" when ADDR_IO,
-- "011" when others;
--
--with data_wr_addr_mask select data_wr_type <=
-- "001" when ADDR_XRAM,
-- "010" when ADDR_IO,
-- "011" when others;
 
--------------------------------------------------------------------------------
-- BRAM interface
 
/trunk/vhdl/mips_pkg.vhdl
1,3 → 1,16
--------------------------------------------------------------------------------
-- mips_pkg.vhdl -- Configuration constants & utility types and functions
--------------------------------------------------------------------------------
-- IMPORTANT:
-- Here's where you define the memory map of the system, in the implementation
-- of function decode_addr.
-- You need to change that function to change the memory map, independent of any
-- additional address decoding you may do out of the FPGA (e.g. if you have more
-- than one chip on any data bus) or out of the MCU module (e.g. when you add
-- new IO registers).
-- Please see the module c2sb_demo and mips_mcu for examples of memory decoding.
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
5,25 → 18,56
 
package mips_pkg is
 
-- FIXME this stuff belongs in the cache module where address decoding is made
-- (besides, they should be module generics, not package constants)
---- Basic types ---------------------------------------------------------------
 
subtype t_word is std_logic_vector(31 downto 0);
 
 
---- System configuration constants --------------------------------------------
 
-- True to use standard-ish MIPS-1 memory map, false to use Plasma's
-- (see implementation of function decode_addr below).
constant USE_MIPS1_ADDR_MAP : boolean := true;
 
-- Reset vector address minus 4 (0xfffffffc for Plasma, 0xbfbffffc for mips1)
constant RESET_VECTOR_M4 : t_word := X"bfbffffc";
 
-- Trap vector address (0x0000003c for Plasma, 0xbfc00180 for mips1)
constant TRAP_VECTOR : t_word := X"bfc00180";
 
 
---- Address decoding ----------------------------------------------------------
 
-- Note: it is the cache module that does all internal address decoding --------
 
-- This is the slice of the address that will be used to decode memory areas
subtype t_addr_decode is std_logic_vector(31 downto 24);
constant ADDR_BOOT : t_addr_decode := X"00";
constant ADDR_XRAM : t_addr_decode := X"80";
constant ADDR_IO : t_addr_decode := X"20";
 
-- 'Attributes' of some memory block -- used when decoding memory addresses
-- type[3] : can_write[1] : cacheable[1] : delay_states[2]
subtype t_range_attr is std_logic_vector(6 downto 0);
-- Part of the memory area attribute: the type of memory determines how the
-- cache module handles each block
subtype t_memory_type is std_logic_vector(2 downto 0);
-- These are all the types the cache knows about
constant MT_BRAM : t_memory_type := "000";
constant MT_IO_SYNC : t_memory_type := "001";
constant MT_SRAM_16B : t_memory_type := "010";
constant MT_FLASH_16B : t_memory_type := "011";
constant MT_DDR_16B : t_memory_type := "100";
constant MT_UNMAPPED : t_memory_type := "111";
 
 
---- More basic types and constants --------------------------------------------
 
subtype t_addr is std_logic_vector(31 downto 0);
subtype t_word is std_logic_vector(31 downto 0);
subtype t_dword is std_logic_vector(63 downto 0);
subtype t_regnum is std_logic_vector(4 downto 0);
 
type t_rbank is array(0 to 31) of t_word;
 
subtype t_pc is std_logic_vector(31 downto 2);
 
-- This is used as a textual shortcut only
constant ZERO : t_word := (others => '0');
 
-- control word for ALU
type t_alu_control is record
logic_sel : std_logic_vector(1 downto 0);
shift_sel : std_logic_vector(1 downto 0);
35,7 → 79,7
use_slt : std_logic;
arith_unsigned : std_logic;
end record t_alu_control;
 
-- Flags coming from the ALU
type t_alu_flags is record
inp1_lt_zero : std_logic;
inp1_eq_zero : std_logic;
59,7 → 103,11
-- CAN BE USED IN SYNTHESIZABLE CODE as long as called with constant arguments
function log2(A : natural) return natural;
 
-- Decodes a memory address, gives the type of memory
-- CAN BE USED IN SYNTHESIZABLE CODE, argument does not need to be constant
function decode_addr(addr : t_addr_decode) return t_range_attr;
 
 
end package;
 
package body mips_pkg is
74,4 → 122,44
return(30);
end function log2;
 
-- Address decoding for Plasma-like system
function decode_addr_plasma(addr : t_addr_decode) return t_range_attr is
begin
 
case addr(31 downto 27) is
when "00000" => return MT_BRAM &"0"&"0"&"00"; -- useg
when "10000" => return MT_SRAM_16B &"1"&"1"&"00"; -- kseg0
when "00100" => return MT_IO_SYNC &"1"&"0"&"00"; -- kseg1 i/o
when others => return MT_UNMAPPED &"0"&"0"&"00"; -- stray
end case;
 
end function decode_addr_plasma;
 
-- Address decoding for MIPS-I-like system
function decode_addr_mips1(addr : t_addr_decode) return t_range_attr is
begin
 
case addr(31 downto 27) is
when "00000" => return MT_SRAM_16B &"1"&"1"&"00"; -- useg
when "10000" => return MT_SRAM_16B &"1"&"1"&"00"; -- kseg0
--when "10100" => return MT_IO_SYNC &"1"&"0"&"00"; -- kseg1 i/o
when "00100" => return MT_IO_SYNC &"1"&"0"&"00"; -- kseg1 i/o
when "10110" => return MT_FLASH_16B&"0"&"0"&"10"; -- kseg1 flash
when "10111" => return MT_BRAM &"0"&"0"&"00"; -- kseg1 boot rom
when others => return MT_UNMAPPED &"0"&"0"&"00"; -- stray
end case;
 
end function decode_addr_mips1;
 
 
function decode_addr(addr : t_addr_decode) return t_range_attr is
begin
if USE_MIPS1_ADDR_MAP then
return decode_addr_mips1(addr);
else
return decode_addr_plasma(addr);
end if;
 
end function decode_addr;
 
end package body;

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