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Rev 6 → Rev 7

/trunk/vhdl_altera_de1/output_files/curl.sof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/vhdl_altera_de1/curl.vhd
1,18 → 1,27
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- http://www.microengineer.eu
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
 
library ieee;
/trunk/vhdl_altera_de1/de1.vhd
1,18 → 1,27
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- http://www.microengineer.eu
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
/trunk/vhdl_altera_de1/index_table.vhd
1,19 → 1,27
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- http://www.microengineer.eu
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
 
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
library ieee;
 
use ieee.std_logic_1164.all;
/trunk/vhdl_altera_de1/spi_slave.vhd
1,18 → 1,27
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- http://www.microengineer.eu
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
 
library ieee;
 
/trunk/vhdl_cyclone10_lp/output_files/curl-cyclone10.sof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/vhdl_cyclone10_lp/curl-cyclone10.qsf
94,19 → 94,20
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name QII_AUTO_PACKED_REGISTERS "MINIMIZE AREA"
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_REGISTER_DUPLICATION OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "EXTRA EFFORT"
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 16.0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/vhdl_cyclone10_lp/curl-cyclone10.qws Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/vhdl_cyclone10_lp/curl.vhd
1,18 → 1,27
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- http://www.microengineer.eu
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
 
library ieee;
43,6 → 52,7
spi_data_rx : in std_logic_vector(31 downto 0);
spi_data_tx : out std_logic_vector(31 downto 0);
spi_data_rxen : in std_logic;
spi_data_strobe : out std_logic;
overflow : out std_logic;
running : out std_logic;
found : out std_logic
63,19 → 73,38
signal curl_state_low : curl_state_array(STATE_LENGTH-1 downto 0);
signal curl_state_high : curl_state_array(STATE_LENGTH-1 downto 0);
 
-- mid state data in 9bit packed format
signal curl_mid_state_low : mid_state_array((STATE_LENGTH/9)-1 downto 0);
signal curl_mid_state_high : mid_state_array((STATE_LENGTH/9)-1 downto 0);
signal data_low : mid_state_array((HASH_LENGTH/DATA_WIDTH)-1 downto 0);
signal data_high : mid_state_array((HASH_LENGTH/DATA_WIDTH)-1 downto 0);
 
 
signal curl_mid_state_low : std_logic_vector(STATE_LENGTH-1 downto 0);
signal curl_mid_state_high : std_logic_vector(STATE_LENGTH-1 downto 0);
 
signal flag_running : std_logic := '0';
signal flag_overflow : std_logic := '0';
signal flag_found : std_logic := '0';
signal flag_start : std_logic := '0';
 
signal flag_curl_finished : std_logic := '0';
 
type binary_nonce_array is array(integer range<>) of unsigned(INTERN_NONCE_LENGTH-1 downto 0);
 
 
signal binary_nonce : unsigned(INTERN_NONCE_LENGTH-1 downto 0);
signal mask : state_vector_type;
signal min_weight_magnitude : min_weight_magnitude_type;
 
signal i_binary_nonce : unsigned(INTERN_NONCE_LENGTH-1 downto 0);
signal tmp_weight_magnitude : min_weight_magnitude_array(0 to PARALLEL-1);
 
signal flag_curl_reset : std_logic;
signal flag_curl_write : std_logic;
signal flag_curl_do_curl : std_logic;
 
signal imask : state_vector_type;
 
 
 
function expand(b : std_logic)
return state_vector_type is
begin
85,7 → 114,8
return (others => '0');
end if;
end expand;
 
 
begin
overflow <= flag_overflow;
running <= flag_running;
101,75 → 131,115
min_weight_magnitude <= (others => '0');
flag_start <= '0';
spi_data_tx <= (others => '0');
-- curl_mid_state_low <= (others => (others => '0'));
-- curl_mid_state_high <= (others => (others => '0'));
addrptr := x"00";
else
flag_start <= '0';
flag_curl_reset <= '0';
flag_curl_write <= '0';
flag_curl_do_curl <= '0';
spi_data_strobe <= '0';
-- new spi data received
if spi_data_rxen = '1' then
spi_cmd := spi_data_rx(31 downto 26);
case spi_cmd is
when "000000" => -- nop (mainly for reading back data)
when "100001" => -- start / stop
when "100000" => -- start / stop
flag_start <= spi_data_rx(0);
when "100101" => -- write to wr address
addrptr := unsigned(spi_data_rx(7 downto 0));
when "100010" => -- write to mid state
if (addrptr <= (STATE_LENGTH/9)-1) then
curl_mid_state_low(to_integer(addrptr)) <= spi_data_rx(DATA_WIDTH-1 downto 0);
curl_mid_state_high(to_integer(addrptr)) <= spi_data_rx(DATA_WIDTH+8 downto DATA_WIDTH);
flag_curl_reset <= spi_data_rx(1);
flag_curl_write <= spi_data_rx(2);
flag_curl_do_curl <= spi_data_rx(3);
when "010000" => -- write to wr address
addrptr := (others => '0'); --unsigned(spi_data_rx(7 downto 0));
when "001000" => -- write to data buffer
if (addrptr <= (HASH_LENGTH/DATA_WIDTH)-1) then
data_low(to_integer(addrptr)) <= spi_data_rx(DATA_WIDTH-1 downto 0);
data_high(to_integer(addrptr)) <= spi_data_rx(DATA_WIDTH+8 downto DATA_WIDTH);
end if;
spi_data_tx <= spi_data_rx;
addrptr := addrptr + 1;
when "100100" =>
when "000100" =>
min_weight_magnitude <= spi_data_rx(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0);
 
when "000001" => -- read flags
spi_data_tx(2 downto 0) <= flag_overflow & flag_found & flag_running;
 
-- for debugging onle ... read back curl_state
-- when "000010" =>
-- spi_addr := spi_data_rx(25 downto 16);
-- spi_data_tx(0+PARALLEL-1 downto 0) <= curl_state_low(to_integer(unsigned(spi_addr)));
-- spi_data_tx(8+PARALLEL-1 downto 8) <= curl_state_high(to_integer(unsigned(spi_addr)));
 
-- for debugging only ... read back mid_state
-- when "000111" =>
-- if (addrptr <= (STATE_LENGTH/9)-1) then
-- spi_data_tx(DATA_WIDTH-1 downto 0) <= curl_mid_state_low(to_integer(addrptr));
-- spi_data_tx(DATA_WIDTH+8 downto DATA_WIDTH) <= curl_mid_state_high(to_integer(addrptr));
-- else
-- spi_data_tx <= (others => '0');
-- end if;
-- addrptr := addrptr + 1; -- dual-used for debugging purposes
when "000011" => -- read nonce
when "000010" => -- read flags
spi_data_tx(3 downto 0) <= flag_curl_finished & flag_overflow & flag_found & flag_running;
spi_data_tx(7 downto 4) <= std_logic_vector(to_unsigned(PARALLEL, 4));
spi_data_tx(8+(PARALLEL-1) downto 8) <= mask;
spi_data_strobe <= '1';
when "000001" => -- read nonce
spi_data_tx(INTERN_NONCE_LENGTH-1 downto 0) <= std_logic_vector(binary_nonce);
when "000100" => -- read mask
spi_data_tx(PARALLEL-1 downto 0) <= mask;
when "010101" => -- loop back read test inverted bits
spi_data_tx <= not spi_data_rx;
when "000110" => -- read back parallel-level
spi_data_tx(3 downto 0) <= std_logic_vector(to_unsigned(PARALLEL, 4));
spi_data_strobe <= '1';
when others =>
spi_data_tx <= (others => '1');
end case;
end case;
end if;
end if;
end if;
end process;
process (clk_slow)
variable state : integer range 0 to 7 := 0;
variable round : integer range 0 to 127 := 0;
variable tmp_index : integer range 0 to 1023;
variable alpha : std_logic_vector(STATE_LENGTH-1 downto 0);
variable beta : std_logic_vector(STATE_LENGTH-1 downto 0);
variable gamma : std_logic_vector(STATE_LENGTH-1 downto 0);
variable delta : std_logic_vector(STATE_LENGTH-1 downto 0);
begin
if rising_edge(clk_slow) then
if reset='1' then
state := 0;
else
case state is
when 0 =>
round := NUMBER_OF_ROUNDS;
flag_curl_finished <= '1';
 
if flag_curl_write = '1' then
for I in 0 to (HASH_LENGTH/DATA_WIDTH)-1 loop
for J in 0 to DATA_WIDTH-1 loop
tmp_index := I*DATA_WIDTH+J;
curl_mid_state_low(tmp_index) <= data_low(I)(J);
curl_mid_state_high(tmp_index) <= data_high(I)(J);
end loop;
end loop;
elsif flag_curl_reset='1' then
curl_mid_state_low <= (others => '1');
curl_mid_state_high <= (others => '1');
end if;
 
if flag_curl_do_curl = '1' then
round := NUMBER_OF_ROUNDS;
flag_curl_finished <= '0';
state := 1;
end if;
when 1 => -- do the curl hash round without any copying needed
if round = 1 then
state := 0;
end if;
for I in 0 to STATE_LENGTH-1 loop
alpha(I) := curl_mid_state_low(index_table(I));
beta(I) := curl_mid_state_high(index_table(I));
gamma(I) := curl_mid_state_high(index_table(I+1));
delta(I) := (alpha(I) or (not gamma(I))) and (curl_mid_state_low(index_table(I+1)) xor beta(I));
 
curl_mid_state_low(I) <= not delta(I);
curl_mid_state_high(I) <= (alpha(I) xor gamma(I)) or delta(I);
end loop;
round := round - 1;
when others =>
state := 0;
end case;
end if;
end if;
end process;
process (clk)
variable state : integer range 0 to 31 := 0;
variable state : integer range 0 to 63 := 0;
variable round : integer range 0 to 127 := 0;
 
variable imask : state_vector_type;
variable i_min_weight_magnitude : min_weight_magnitude_type;
variable tmp_weight_magnitude : min_weight_magnitude_array(0 to PARALLEL-1);
variable i_binary_nonce : unsigned(INTERN_NONCE_LENGTH-1 downto 0);
 
-- temporary registers get optimized away
variable alpha : curl_state_array(STATE_LENGTH-1 downto 0);
176,8 → 246,7
variable beta : curl_state_array(STATE_LENGTH-1 downto 0);
variable gamma : curl_state_array(STATE_LENGTH-1 downto 0);
variable delta : curl_state_array(STATE_LENGTH-1 downto 0);
variable tmp_index : integer range 0 to 1023;
 
variable tmp_highest_bit : integer range 0 to 31;
begin
if rising_edge(clk) then
192,43 → 261,59
-- curl_state_low <= (others => (others => '0'));
-- curl_state_high <= (others => (others => '0'));
-- tmp_weight_magnitude := (others => (others => '0'));
i_binary_nonce := (others => '0');
imask := (others => '0');
i_min_weight_magnitude := (others => '0');
alpha := (others => (others => '0'));
beta := (others => (others => '0'));
gamma := (others => (others => '0'));
delta := (others => (others => '0'));
tmp_index := 0;
i_binary_nonce <= (others => '0');
imask <= (others => '0');
-- i_min_weight_magnitude := (others => '0');
-- alpha := (others => (others => '0'));
-- beta := (others => (others => '0'));
-- gamma := (others => (others => '0'));
-- delta := (others => (others => '0'));
-- tmp_index := 0;
tmp_weight_magnitude <= (others => (others => '0'));
else
case state is
when 0 =>
mask <= imask;
binary_nonce <= i_binary_nonce;
flag_running <= '0';
when others =>
flag_running <= '1';
end case;
case state is
when 0 =>
-- flag_running <= '0';
if flag_start = '1' then
i_binary_nonce := x"00000000";
i_min_weight_magnitude := min_weight_magnitude;
i_binary_nonce <= x"00000000";
-- flag_running <= '1';
state := 1;
end if;
-- nop until start from spi
when 1 =>
-- do PoW
when 1 => -- copy mid state and insert nonce
i_min_weight_magnitude := min_weight_magnitude;
flag_found <= '0';
flag_running <= '1';
flag_overflow <= '0';
state := 8;
when 8 => -- copy mid state and insert nonce
binary_nonce <= i_binary_nonce;
-- pipelining
i_binary_nonce <= i_binary_nonce + 1;
 
-- -- copy and fully expand mid-state to curl-state
for I in 0 to STATE_LENGTH-1 loop
if I < NONCE_OFFSET or I > NONCE_OFFSET + NONCE_LENGTH - 1 then
curl_state_low(I) <= expand(curl_mid_state_low(I));
curl_state_high(I) <= expand(curl_mid_state_high(I));
end if;
end loop;
 
-- for I in 0 to NONCE_OFFSET-1 loop
-- curl_state_low(I) <= expand(curl_mid_state_low(I));
-- curl_state_high(I) <= expand(curl_mid_state_high(I));
-- end loop;
--
-- for I in NONCE_OFFSET + NONCE_LENGTH to STATE_LENGTH-1 loop
-- curl_state_low(I) <= expand(curl_mid_state_low(I));
-- curl_state_high(I) <= expand(curl_mid_state_high(I));
-- end loop;
-- copy and fully expand mid-state to curl-state
for I in 0 to (STATE_LENGTH/DATA_WIDTH)-1 loop
for J in 0 to DATA_WIDTH-1 loop
tmp_index := I*DATA_WIDTH+J;
if tmp_index < NONCE_OFFSET or tmp_index > NONCE_OFFSET + NONCE_LENGTH - 1 then
curl_state_low(tmp_index) <= expand(curl_mid_state_low(I)(J));
curl_state_high(tmp_index) <= expand(curl_mid_state_high(I)(J));
end if;
end loop;
end loop;
-- fill all ... synthesizer is smart enough to optimize away what is not needed
for I in NONCE_OFFSET to NONCE_OFFSET + NONCE_LENGTH - 1 loop
267,11 → 352,15
 
-- initialize round-counter
round := NUMBER_OF_ROUNDS;
state := 10;
when 10 => -- do the curl hash round without any copying needed
if i_binary_nonce = x"ffffffff" then
flag_overflow <= '1';
state := 0;
else
state := 2;
end if;
when 2 => -- do the curl hash round without any copying needed
if round = 1 then
state := 16;
state := 3;
end if;
for I in 0 to STATE_LENGTH-1 loop
alpha(I) := curl_state_low(index_table(I));
284,37 → 373,32
curl_state_high(I) <= (alpha(I) xor gamma(I)) or delta(I);
end loop;
round := round - 1;
when 16 => -- find out which solution - if any
imask := (others => '0');
when 3 => -- find out which solution - if any
-- transform "vertical" trits to "horizontal" bits
-- and compare with min weight magnitude mask
for I in 0 to PARALLEL-1 loop
tmp_weight_magnitude(I) := (others => '0');
for J in 0 to BITS_MIN_WEIGHT_MAGINUTE_MAX-1 loop
tmp_weight_magnitude(I)(J) := curl_state_low(HASH_LENGTH - 1 - J)(I) and curl_state_high(HASH_LENGTH - 1 - J)(I);
tmp_weight_magnitude(I)(J) <= curl_state_low(HASH_LENGTH - 1 - J)(I) and curl_state_high(HASH_LENGTH - 1 - J)(I) and i_min_weight_magnitude(J);
end loop;
tmp_weight_magnitude(I) := tmp_weight_magnitude(I) and i_min_weight_magnitude; -- only consider used bits
end loop;
 
-- pipelining
imask <= (others => '0');
for I in 0 to PARALLEL-1 loop
if tmp_weight_magnitude(I) = i_min_weight_magnitude then
imask(I) := '1';
imask(I) <= '1';
end if;
end loop;
state := 17;
when 17 =>
if unsigned(imask) /= 0 then
state := 30;
elsif i_binary_nonce = x"ffffffff" then
state := 31;
-- pipelining
if unsigned(imask) = 0 then
state :=1;
else
i_binary_nonce := i_binary_nonce + 1;
state := 8;
flag_found <= '1';
mask <= imask;
state :=0;
end if;
when 30 =>
flag_found <= '1';
state := 0;
when 31 =>
flag_overflow <= '1';
state := 0;
when others =>
state := 0;
end case;
/trunk/vhdl_cyclone10_lp/de1.vhd
1,3 → 1,28
-- IOTA Pearl Diver VHDL Port
--
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
21,6 → 46,7
 
architecture beh of de1 is
 
signal nreset : std_logic;
 
 
 
31,8 → 57,8
signal spi_data_tx : std_logic_vector(31 downto 0);
signal spi_data_rx : std_logic_vector(31 downto 0);
signal spi_data_rx_en : std_logic;
signal spi_data_strobe : std_logic;
 
 
signal pll_slow : std_logic;
 
component spi_slave
45,6 → 71,7
miso : out std_logic;
sck : in std_logic;
ss : in std_logic;
data_strobe : in std_logic;
data_rd : in std_logic_vector(31 downto 0);
74,6 → 101,7
spi_data_rx : in std_logic_vector(31 downto 0);
spi_data_tx : out std_logic_vector(31 downto 0);
spi_data_rxen : in std_logic;
spi_data_strobe : out std_logic;
 
overflow : out std_logic;
running : out std_logic;
82,6 → 110,9
end component;
 
begin
nreset <= not reset;
 
 
pll0 : pll port map (
areset => pll_reset,
inclk0 => CLOCK_50,
93,12 → 124,13
spi0 : spi_slave port map (
clk => pll_slow,
reset => reset,
reset => nreset,
mosi => spi_mosi,
miso => spi_miso,
sck => spi_sck,
ss => spi_ss,
data_strobe => spi_data_strobe,
data_rd => spi_data_tx,
data_wr => spi_data_rx,
107,12 → 139,13
curl0 : curl port map (
clk => pll_clk,
reset => reset,
reset => nreset,
clk_slow => pll_slow,
spi_data_rx => spi_data_rx,
spi_data_tx => spi_data_tx,
spi_data_rxen => spi_data_rx_en,
spi_data_strobe => spi_data_strobe,
overflow => led_overflow,
running => led_running,
/trunk/vhdl_cyclone10_lp/index_table.vhd
1,3 → 1,28
-- IOTA Pearl Diver VHDL Port
--
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
 
library ieee;
 
use ieee.std_logic_1164.all;
/trunk/vhdl_cyclone10_lp/pll.vhd
148,13 → 148,13
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_divide_by => 25,
clk0_duty_cycle => 50,
clk0_multiply_by => 7,
clk0_multiply_by => 94,
clk0_phase_shift => "0",
clk1_divide_by => 4,
clk1_divide_by => 25,
clk1_duty_cycle => 50,
clk1_multiply_by => 7,
clk1_multiply_by => 47,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
241,8 → 241,8
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "175.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "87.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "188.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "94.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
270,10 → 270,10
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "175.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "70.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "188.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "94.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
317,13 → 317,13
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "94"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
/trunk/vhdl_cyclone10_lp/spi_slave.vhd
1,19 → 1,29
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
-- http://microengineer.eu
-- discord: pmaxuw#8292
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
--
-- http://www.microengineer.eu
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
 
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
library ieee;
 
use ieee.std_logic_1164.all;
34,7 → 44,8
data_rd : in std_logic_vector(31 downto 0);
data_wr : out std_logic_vector(31 downto 0);
data_wren : out std_logic
data_wren : out std_logic;
data_strobe : in std_logic
);
end spi_slave;
67,9 → 78,13
sync_sck <= sync_sck(0) & sck;
sync_ss <= sync_ss(0) & ss;
 
if data_strobe = '1' then
i_shiftregister := data_rd;
end if;
case sync_ss is
when "11" =>
i_shiftregister := data_rd;
-- i_shiftregister := data_rd;
cnt := 0;
-- i_flip := '0';
when "10" =>
81,7 → 96,7
when "00" =>
case sync_sck is
when "01" =>
i_shiftregister := i_shiftregister(30 downto 0) & sync_mosi(0);
i_shiftregister := i_shiftregister(30 downto 0) & mosi;
cnt := cnt + 1;
when "10" =>
miso <= i_shiftregister(31);

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