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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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    /iso7816_3_master/trunk/sources
    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/Uart.v
1,25 → 1,53
/*
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 08/31/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 23:57:02 08/31/2010
// Design Name:
// Module Name: Uart
// Project Name:
// Target Devices:
// Tool versions:
// Description: Half duplex UART with 1 byte buffer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BasicHalfDuplexUart(
 
/*
Half duplex UART with 1 byte buffer
*/
module BasicHalfDuplexUart
#(//parameters to override
parameter DIVIDER_WIDTH = 1,
parameter CLOCK_PER_BIT_WIDTH = 13, //allow to support default speed of ISO7816
//invert the polarity of the output or not
parameter IN_POLARITY = 1'b0,
parameter PARITY_POLARITY = 1'b1,
//default conventions
parameter START_BIT = 1'b0,
parameter STOP_BIT1 = 1'b1,
parameter STOP_BIT2 = 1'b1
)
(
output wire [7:0] rxData,
output wire overrunErrorFlag, //new data has been received before dataOut was read
output wire dataOutReadyFlag, //new data available
47,17 → 75,6
input wire nReset
);
 
//parameters to override
parameter DIVIDER_WIDTH = 1;
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
//invert the polarity of the output or not
parameter IN_POLARITY = 1'b0;
parameter PARITY_POLARITY = 1'b1;
//default conventions
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT2 = 1'b1;
 
//constant definition for states
localparam IDLE_STATE = 3'b000;
localparam RX_STATE = 3'b001;
141,3 → 158,4
);
 
endmodule
`default_nettype wire
/Iso7816_3_Master.v
1,15 → 1,35
`timescale 1ns / 1ps
/*
Author: Sebastien Riou (acapola)
Creation date: 17:16:40 01/09/2011
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Author: Sebastien Riou
// Creation date: 17:16:40 01/09/2011
//
// Last change date: $LastChangedDate$
// Last changed by: $LastChangedBy$
// Last revision: $LastChangedRevision$
// Head URL: $HeadURL$
//
//////////////////////////////////////////////////////////////////////////////////
module Iso7816_3_Master(
input wire nReset,
input wire clk,
114,3 → 134,4
end
end
endmodule
`default_nettype wire
/RxCoreSpec.v
1,37 → 1,38
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 23:57:02 09/04/2010
// Design Name:
// Module Name: RxCore2
// Project Name:
// Target Devices:
// Tool versions:
// Description: non synthetizable model used as reference in test bench
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
module Delay();
/*
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 09/04/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
task WaitClocks;
input [CLOCK_PER_BIT_WIDTH-1:0] limit;
integer bitClocksCounter;
begin
for(bitClocksCounter=0;bitClocksCounter<limit;bitClocksCounter=bitClocksCounter+1) begin
@(posedge syncClk);
end
end
endtask
All rights reserved.
 
endmodule
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
 
/*
non synthetizable model used as reference in test bench
*/
 
module RxCoreSpec(
366,3 → 367,4
end
 
endmodule
`default_nettype wire
/Counter.v
1,25 → 1,45
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 23:57:02 08/31/2010
// Design Name:
// Module Name: Counter
// Project Name:
// Target Devices:
// Tool versions:
// Description: A counter with increment and clear operation
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Counter(
/*
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 08/31/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
/*
A counter with increment and clear operation
*/
module Counter
#(//parameters to override
parameter DIVIDER_WIDTH = 16,
parameter WIDTH = 8,
parameter WIDTH_INIT = 1
)
(
output reg [WIDTH-1:0] counter,
output wire earlyMatch,
output reg match,
32,11 → 52,6
input wire clk,
input wire nReset
);
 
//parameters to override
parameter DIVIDER_WIDTH = 16;
parameter WIDTH = 8;
parameter WIDTH_INIT = 1;
 
wire divideBy1;
wire divMatch;
87,3 → 102,4
end
 
endmodule
`default_nettype wire
/ClkDivider.v
1,24 → 1,35
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 18:05:27 01/09/2011
// Design Name:
// Module Name: clkDivider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
Author: Sebastien Riou (acapola)
Creation date: 18:05:27 01/09/2011
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
/*
Basic clock divider
 
33,18 → 44,21
1. set it to 0 at least for one cycle
2. set it to the new value.
*/
module ClkDivider(
input nReset,
input clk, // input clock
input [DIVIDER_WIDTH-1:0] divider, // divide factor
output dividedClk, // divided clock
output divideBy1,
output match,
output risingMatch,
output fallingMatch
module ClkDivider
#(//parameters to override
parameter DIVIDER_WIDTH = 16
)
(
input wire nReset,
input wire clk, // input clock
input wire [DIVIDER_WIDTH-1:0] divider, // divide factor
output wire dividedClk, // divided clock
output wire divideBy1,
output wire match,
output wire risingMatch,
output wire fallingMatch
);
//parameters to override
parameter DIVIDER_WIDTH = 16;
 
reg out;//internal divided clock
reg [DIVIDER_WIDTH-1:0] cnt;
73,3 → 87,4
end
 
endmodule
`default_nettype wire
/RxCoreSelfContained.v
1,25 → 1,48
/*
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 08/31/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 23:57:02 08/31/2010
// Design Name:
// Module Name: RxCore
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RxCoreSelfContained(
 
module RxCoreSelfContained
#(//parameters to override
parameter DIVIDER_WIDTH = 1,
parameter CLOCK_PER_BIT_WIDTH = 13, //allow to support default speed of ISO7816
parameter PRECISE_STOP_BIT = 0, //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
//default conventions
parameter START_BIT = 1'b0,
parameter STOP_BIT1 = 1'b1,
parameter STOP_BIT2 = 1'b1
)
(
output wire [7:0] dataOut,
output wire overrunErrorFlag, //new data has been received before dataOut was read
output wire dataOutReadyFlag, //new data available
40,18 → 63,6
input wire nReset
);
 
//parameters to override
parameter DIVIDER_WIDTH = 1;
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
//invert the polarity of the output or not
//parameter IN_POLARITY = 1'b0;
//parameter PARITY_POLARITY = 1'b1;
//default conventions
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT2 = 1'b1;
 
wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter;
wire bitClocksCounterEarlyMatch;
wire bitClocksCounterMatch;
106,3 → 117,4
);
 
endmodule
`default_nettype wire
/RxCore.v
1,24 → 1,37
/*
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 08/31/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 23:57:02 08/31/2010
// Design Name:
// Module Name: RxCore
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module RxCore(
output reg [7:0] dataOut,
output reg overrunErrorFlag, //new data has been received before dataOut was read
250,3 → 263,4
end
 
endmodule
`default_nettype wire
/TxCore.v
1,25 → 1,46
/*
Author: Sebastien Riou (acapola)
Creation date: 21:16:10 08/29/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
//
// Create Date: 21:16:10 08/29/2010
// Design Name:
// Module Name: TxCore
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module TxCore(
 
module TxCore
#(//parameters to override
parameter DIVIDER_WIDTH = 1,
parameter CLOCK_PER_BIT_WIDTH = 13,//allow to support default speed of ISO7816
//default conventions
parameter START_BIT = 1'b0,
parameter STOP_BIT1 = 1'b1
)
(
output wire comClk,
output wire serialOut,
output wire run,
36,13 → 57,6
input wire nReset
);
 
//parameters to override
parameter DIVIDER_WIDTH = 1;
parameter CLOCK_PER_BIT_WIDTH = 13;//allow to support default speed of ISO7816
//default conventions
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
 
//constant definition for state
localparam IDLE_STATE = 0;
localparam START_STATE = 1;
178,3 → 192,4
end
 
endmodule
`default_nettype wire
/HalfDuplexUartIf.v
1,25 → 1,42
`timescale 1ns / 1ps
/*
Author: Sebastien Riou (acapola)
Creation date: 19:57:35 10/31/2010
 
$LastChangedDate$
$LastChangedBy$
$LastChangedRevision$
$HeadURL$
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:57:35 10/31/2010
// Design Name:
// Module Name: HalfDuplexUartIf
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HalfDuplexUartIf(
 
module HalfDuplexUartIf
#(//parameters to override
parameter DIVIDER_WIDTH = 1,
parameter CLOCK_PER_BIT_WIDTH = 13 //allow to support default speed of ISO7816
)
(
input wire nReset,
input wire clk,
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
34,9 → 51,7
output wire serialOut,
output wire comClk
);
//parameters to override
parameter DIVIDER_WIDTH = 1;
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
 
 
reg [7:0] dataReg;
 
138,3 → 153,4
);
 
endmodule
`default_nettype wire

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