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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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  • This comparison shows the changes necessary to convert path 
    /iso7816_3_master/trunk/sources
    from Rev 12 to Rev 15
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Rev 12 → Rev 15

/Uart.v
83,11 → 83,20
assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
 
reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
reg safeStopBit2;
reg safeOddParity;
reg safeMsbFirst;
always @(posedge clk, negedge nReset) begin
if(~nReset) begin
safeClocksPerBit<=clocksPerBit;
safeStopBit2<=stopBit2;
safeOddParity<=oddParity;
safeMsbFirst<=msbFirst;
end else if(endOfRx|endOfTx|~(rxRun|rxStartBit|txRun)) begin
safeClocksPerBit<=clocksPerBit;
safeStopBit2<=stopBit2;
safeOddParity<=oddParity;
safeMsbFirst<=msbFirst;
end
end
 
108,9 → 117,9
.stopBit(stopBit),
.clkPerCycle(clkPerCycle),
.clocksPerBit(safeClocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
.stopBit2(safeStopBit2),
.oddParity(safeOddParity),
.msbFirst(safeMsbFirst),
.ackFlags(ackFlags),
.serialIn(rxSerialIn),
.comClk(comClk),
129,9 → 138,9
.dataIn(txData),
.clkPerCycle(clkPerCycle),
.clocksPerBit(safeClocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
.stopBit2(safeStopBit2),
.oddParity(safeOddParity),
.msbFirst(safeMsbFirst),
.loadDataIn(loadDataIn),
.comClk(comClk),
.clk(clk),
/Iso7816_3_Master.v
39,7 → 39,7
input wire [7:0] dataIn,
input wire nWeDataIn,
input wire [12:0] cyclesPerEtu,
output wire [7:0] dataOut,
output reg [7:0] dataOut,
input wire nCsDataOut,
output wire [7:0] statusOut,
input wire nCsStatusOut,
64,6 → 64,16
pullup(isoSio);
wire comClk;
 
wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
wire sioHighValue = ~useIndirectConvention;//apply only to data bits
 
wire [7:0] uart_dataOut;
wire [7:0] uart_dataIn = sioHighValue ? dataIn : ~dataIn;
always @(*) dataOut = sioHighValue ? uart_dataOut : ~uart_dataOut;
 
 
HalfDuplexUartIf #(
.DIVIDER_WIDTH(1'b1),
.CLOCK_PER_BIT_WIDTH(4'd13)
72,10 → 82,13
.nReset(nReset),
.clk(clk),
.clkPerCycle(1'b0),
.dataIn(dataIn),
.dataIn(uart_dataIn),
.nWeDataIn(nWeDataIn),
.clocksPerBit(cyclesPerEtu),
.dataOut(dataOut),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
.dataOut(uart_dataOut),
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
.nCsStatusOut(nCsStatusOut),
107,7 → 120,11
if(waitTs) begin
if(statusOut[0]) begin
waitTs<=1'b0;
ts<=dataOut;
case(dataOut)
8'h3B: ts<=dataOut;
8'h03: ts<=8'h3F;
default: ts<=dataOut;
endcase
end
resetCnt<=resetCnt+1;
end
/HalfDuplexUartIf.v
43,7 → 43,10
input wire [7:0] dataIn,
input wire nWeDataIn,
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
output wire [7:0] dataOut,
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
output wire [7:0] dataOut,
input wire nCsDataOut,
output wire [7:0] statusOut,
input wire nCsStatusOut,
57,10 → 60,6
 
// Inputs
wire [7:0] txData;
//wire [12:0] clocksPerBit;
wire stopBit2=1;
wire oddParity=0; //if 1, parity bit is such that data+parity have an odd number of 1
wire msbFirst=0; //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
reg txPending;
wire ackFlags;
 
81,8 → 80,7
reg [1:0] flagsReg;
assign txData = dataReg;
//assign clocksPerBit = 7;
 
assign dataOut=dataReg;
assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
 

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