URL
https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
Subversion Repositories iso7816_3_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/iso7816_3_master/trunk/test
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/ComTxDriverTasks.v
1,3 → 1,35
/* |
Author: Sebastien Riou (acapola) |
Creation date: 17:16:40 01/09/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`include "HexStringConversion.v" |
|
//low level tasks |
/tb_BasicHalfDuplexUart.v
1,27 → 1,37
/* |
Author: Sebastien Riou (acapola) |
Creation date: 19:45:19 10/31/2010 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:45:19 10/31/2010 |
// Design Name: BasicHalfDuplexUart |
// Module Name: /home/seb/dev/hardware/Uart/tb_BasicHalfDuplexUart.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: BasicHalfDuplexUart |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module tb_BasicHalfDuplexUart; |
|
// Inputs |
84,4 → 94,5
end |
|
endmodule |
`default_nettype wire |
|
/FiDiAnalyzer.v
1,6 → 1,37
`timescale 1ns / 1ps |
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:22:43 01/10/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
|
|
module FiDiAnalyzer( |
input wire [3:0] fiCode, |
input wire [3:0] diCode, |
181,4 → 212,5
end |
|
endmodule |
`default_nettype wire |
|
/HexStringConversion.v
1,3 → 1,35
/* |
Author: Sebastien Riou (acapola) |
Creation date: 17:16:40 01/09/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
|
function [7:0] hexString2Byte; |
input [15:0] byteInHexString; |
/DummyCard.v
1,26 → 1,35
`timescale 1ns / 1ps |
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:22:43 01/10/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 22:22:43 01/10/2011 |
// Design Name: HalfDuplexUartIf |
// Module Name: dummyCard.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module DummyCard( |
input wire isoReset, |
143,17 → 152,33
sendHexBytes("3B00"); |
waitEndOfTx; |
end else begin |
//get tpdu |
for(i=0;i<5;i=i+1) |
//get CLA |
receiveByte(tpduHeader[CLA_I+:8]); |
|
//get INS~P2 or PPS |
for(i=1;i<4;i=i+1) |
receiveByte(tpduHeader[(CLA_I-(i*8))+:8]); |
//dispatch |
case(tpduHeader[7+CLA_I:P2_I]) |
32'h000C0000: writeBufferCmd; |
32'h000A0000: readBufferCmd; |
default: sendHexBytes("6986");//sendWord(16'h6986); |
endcase |
|
if(8'hFF==tpduHeader[CLA_I+:8]) begin |
//support only PPS8 for the time being |
if(32'hFF789778==tpduHeader[7+CLA_I:P2_I]) begin |
sendHexBytes("FF789778"); |
waitEndOfTx; |
cyclesPerEtu <= 13'd8-1'b1; |
end |
end else begin |
//tpdu: get P3 |
receiveByte(tpduHeader[P3_I+:8]); |
//dispatch |
case(tpduHeader[7+CLA_I:P2_I]) |
32'h000C0000: writeBufferCmd; |
32'h000A0000: readBufferCmd; |
default: sendHexBytes("6986");//sendWord(16'h6986); |
endcase |
end |
end |
end |
|
endmodule |
`default_nettype wire |
|
/TriWire.v
1,5 → 1,37
/* |
Author: Sebastien Riou (acapola) |
Creation date: 14:22:43 01/29/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
`default_nettype none |
|
/***************************************************************** |
* module triwire: bidirectional wire bus model with delay |
* |
71,3 → 103,4
(b*>a)=(1,1); |
endspecify |
endmodule */ |
`default_nettype wire |
/HammingWeight.v
1,5 → 1,34
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:22:43 01/10/2011 |
|
`timescale 1ns / 1ps |
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
|
module HammingWeight( |
20,36 → 49,4
end |
end |
endmodule |
|
/* |
task hammingWeight |
parameter DATA_WIDTH=4; |
parameter WEIGHT_WIDTH=2; |
input wire [DATA_WIDTH-1:0] dataIn; |
output reg [WEIGHT_WIDTH-1:0] hammingWeight; |
integer i; |
begin |
|
for(i=0;i<DATA_WIDTH;i=i+1) begin |
hammingWeight=hammingWeight + dataIn[i]; |
end |
|
end |
endtask |
*/ |
/* |
function hammingWeight |
parameter DATA_WIDTH=4; |
parameter WEIGHT_WIDTH=2; |
input wire [DATA_WIDTH-1:0] dataIn; |
output reg [WEIGHT_WIDTH-1:0] hammingWeight; |
integer i; |
begin |
|
for(i=0;i<DATA_WIDTH;i=i+1) begin |
hammingWeight=hammingWeight + dataIn[i]; |
end |
|
end |
endtask |
*/ |
`default_nettype wire |
/tb_HalfDuplexUartIf.v
1,27 → 1,37
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:45:51 10/31/2010 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 22:45:51 10/31/2010 |
// Design Name: HalfDuplexUartIf |
// Module Name: tb_HalfDuplexUartIf.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module tb_HalfDuplexUartIf; |
parameter CLK_PERIOD = 10;//should be %2 |
parameter DIVIDER_WIDTH = 16; |
272,4 → 282,5
|
|
endmodule |
`default_nettype wire |
|
/tsAnalyzer.v
1,5 → 1,36
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:22:43 01/10/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
`default_nettype none |
|
module TsAnalyzer( |
input wire nReset, |
53,4 → 84,5
end |
|
endmodule |
`default_nettype wire |
|
/ComDriverTasks.v
1,3 → 1,35
/* |
Author: Sebastien Riou (acapola) |
Creation date: 17:16:40 01/09/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`include "ComRxDriverTasks.v" |
`include "ComTxDriverTasks.v" |
|
/RxCoreTestBench.v
1,27 → 1,37
/* |
Author: Sebastien Riou (acapola) |
Creation date: 21:02:24 09/02/2010 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 21:02:24 09/02/2010 |
// Design Name: RxCore |
// Module Name: tb_RxCore.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: RxCore |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module tb_RxCoreComparator( |
output reg implMismatch, |
output [7:0] dataOut, |
664,4 → 674,5
|
|
endmodule |
`default_nettype wire |
|
/tbIso7816_3_Master.v
1,26 → 1,36
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:16:42 01/10/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
`default_nettype none |
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: Sebastien Riou |
// |
// Create Date: 22:16:42 01/10/2011 |
// Design Name: Iso7816_3_Master |
// Module Name: tbIso7816_3_Master.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: Iso7816_3_Master |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module tbIso7816_3_Master; |
parameter CLK_PERIOD = 10;//should be %2 |
163,8 → 173,10
|
|
integer tbErrorCnt; |
reg tbTestSequenceDone; |
initial begin |
// Initialize Inputs |
tbErrorCnt=0; |
COM_errorCnt=0; |
nReset = 0; |
clk = 0; |
200,22 → 212,24
end |
@(posedge clk); |
end |
$display("Two cycle pause in communication detected, stop simulation, time=",$time); |
#(CLK_PERIOD*372*12); |
$finish; |
if(1'b1!==tbTestSequenceDone) begin |
$display("ERROR: Two cycle pause in communication detected, stop simulation, time=",$time); |
#(CLK_PERIOD*372*12); |
$finish; |
end |
end |
//T=0 tpdu stimuli |
initial begin |
//receiveAndCheckByte(8'h3B); |
//receiveAndCheckByte(8'h00); |
tbTestSequenceDone=1'b0; |
receiveAndCheckHexBytes("3B00"); |
sendHexBytes("000C000001"); |
//receiveAndCheckByte(8'h0C); |
receiveAndCheckHexBytes("0C"); |
sendHexBytes("55"); |
//receiveAndCheckByte(8'h90); |
//receiveAndCheckByte(8'h00); |
receiveAndCheckHexBytes("9000"); |
tbTestSequenceDone=1'b1; |
$display("SUCCESS: test sequence completed."); |
#(CLK_PERIOD*372*12); |
$finish; |
end |
initial begin |
// timeout |
228,4 → 242,5
always |
#(CLK_PERIOD/2) clk = ! clk; |
endmodule |
`default_nettype wire |
|
/TxCoreTestBench.v
1,27 → 1,37
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:53:00 08/29/2010 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: Sebastien Riou |
// |
// Create Date: 22:53:00 08/29/2010 |
// Design Name: TxCore |
// Module Name: tb_TxCore.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: TxCore |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module tb_TxCore; |
parameter PARITY = 1; |
parameter CLK_PERIOD = 10;//should be %2 |
99,4 → 109,5
#(CLK_PERIOD/2) clk = ! clk; |
|
endmodule |
`default_nettype wire |
|
/Iso7816_directionProbe.v
1,26 → 1,54
`timescale 1ns / 1ps |
`default_nettype none |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: Sebastien Riou |
// |
// Create Date: 17:14:04 01/29/2011 |
// Design Name: |
// Module Name: Iso7816_directionProbe |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: model a probe which consist only of wires. Propagation delay over the sio line |
// is used to determined the direction of the communication: |
// If the terminal send a start bit, the termMon output will go low before cardMon and viceversa |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
/* |
Author: Sebastien Riou (acapola) |
Creation date: 17:14:04 01/29/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
/* |
Models a probe which consist only of wires. Propagation delay over the sio line |
is used to determined the direction of the communication: |
If the terminal send a start bit, the termMon output will go low before cardMon and viceversa: |
|
sio line |
Terminal ---------------------------------- Card |
| | |
| | |
termMon cardMon |
|
Note for a physical implementation: |
The difference between the delay "Terminal to termMon" and the delay "Card to cardMon" |
should be kept small in comparison to the delay "Terminal to/from Card" (considering falling edge delay) |
|
In this model, delays are 0 except the delay over the sio line. |
*/ |
module Iso7816_directionProbe( |
inout wire isoSioTerm, |
inout wire isoSioCard, |
33,3 → 61,4
assign cardMon = isoSioCard; |
|
endmodule |
`default_nettype wire |
/ComRxDriverTasks.v
1,4 → 1,35
/* |
Author: Sebastien Riou (acapola) |
Creation date: 17:16:40 01/09/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
//wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull; |
//assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = COM_statusOut; |
|
/iso7816_3_t0_analyzer.v
1,6 → 1,37
`timescale 1ns / 1ps |
/* |
Author: Sebastien Riou (acapola) |
Creation date: 22:22:43 01/10/2011 |
|
$LastChangedDate$ |
$LastChangedBy$ |
$LastChangedRevision$ |
$HeadURL$ |
|
This file is under the BSD licence: |
Copyright (c) 2011, Sebastien Riou |
|
All rights reserved. |
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission. |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
`default_nettype none |
|
|
module Iso7816_3_t0_analyzer |
#(parameter DIVIDER_WIDTH = 1) |
( |
367,4 → 398,5
assign termTx = useDirectionProbe ? phy_termTx : proto_termTx; |
|
endmodule |
`default_nettype wire |
|