URL
https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
Subversion Repositories iso7816_3_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/iso7816_3_master/trunk/test
- from Rev 18 to Rev 19
- ↔ Reverse comparison
Rev 18 → Rev 19
/DummyCard.v
109,6 → 109,7
/*T=0 card model |
|
ATR: |
3B/3F 90 97 40 20 |
3B/3F 94 97 80 1F 42 BA BE BA BE |
3B 9E 96 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 0D |
|
188,9 → 189,10
sendHexBytes("3F"); |
else |
sendHexBytes("3B"); |
sendHexBytes("90974020"); |
//sendHexBytes("9497801F42BABEBABE"); |
//sendHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 0D"); |
sendHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 "); |
//sendHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 "); |
waitEndOfTx; |
end else begin |
//get CLA |
/tbIso7816_3_Master.v
242,8 → 242,9
//receiveAndCheckHexBytes("3B00"); |
receiveByte(bytesFromCard[7:0]);//3B or 3F, so we don't check (Master and Spy do) |
//receiveAndCheckHexBytes("9497801F42BABEBABE"); |
receiveAndCheckHexBytes("90974020"); |
//TODO: handle TCK-->receiveAndCheckHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00 0D"); |
receiveAndCheckHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00"); |
//receiveAndCheckHexBytes("9E 97 80 1F C7 80 31 E0 73 FE 21 1B 66 D0 00 28 24 01 00"); |
sendHexBytes("FF109778"); |
receiveAndCheckHexBytes("FF109778"); |
cyclesPerEtu=8-1; |
/iso7816_3_t0_analyzer.v
98,7 → 98,7
//wire txRun=1'b0; |
|
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull; |
//assign overrunErrorFlag = overrunError; |
assign overrunErrorFlag = overrunError; |
assign frameErrorFlag = frameError; |
|
wire [7:0] rxData; |
254,14 → 254,23
end |
tempBytesCnt <= 2'h0; |
tdiStruct <= {tdiCnt+1'b1,dataOut}; |
if(12'h0=={dataOut,atrK}) begin |
atrCompleted <= 1'b1; |
{waitCardTx,waitTermTx}<=2'b01; |
end |
//if(12'h0=={dataOut,atrK}) begin |
// atrCompleted <= 1'b1; |
// {waitCardTx,waitTermTx}<=2'b01; |
//end |
if((1'b0==tdiStruct[7]) |//we just received the last interface byte |
(4'b0==dataOut[7:4])) begin //or new TDi indicate no further interface bytes |
fsmState <= (4'b0!=earlyAtrK) ? ATR_HISTORICAL : |
atrHasTck ? ATR_TCK : T0_HEADER; |
//fsmState <= (4'b0!=earlyAtrK) ? ATR_HISTORICAL : |
// atrHasTck ? ATR_TCK : T0_HEADER; |
if(4'b0!=earlyAtrK) begin |
fsmState <= ATR_HISTORICAL; |
end else if(atrHasTck) begin |
fsmState <= ATR_TCK; |
end else begin |
fsmState <= T0_HEADER; |
atrCompleted <= 1'b1; |
{waitCardTx,waitTermTx}<=2'b01; |
end |
end else begin//TDi, i from 1 to 15 |
fsmState <= ATR_TDI; |
end |