URL
https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
Subversion Repositories iso7816_3_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/iso7816_3_master/trunk/test
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/tb_HalfDuplexUartIf.v
6,7 → 6,7
// |
// Create Date: 22:45:51 10/31/2010 |
// Design Name: HalfDuplexUartIf |
// Module Name: /home/seb/dev/hardware/Uart/tb_HalfDuplexUartIf.v |
// Module Name: tb_HalfDuplexUartIf.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
/RxCoreTestBench.v
6,7 → 6,7
// |
// Create Date: 21:02:24 09/02/2010 |
// Design Name: RxCore |
// Module Name: D:/Hardware/Uart/tb_RxCore.v |
// Module Name: tb_RxCore.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
/tbIso7816_3_Master.v
0,0 → 1,123
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 22:16:42 01/10/2011 |
// Design Name: Iso7816_3_Master |
// Module Name: tbIso7816_3_Master.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: Iso7816_3_Master |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module tbIso7816_3_Master; |
parameter CLK_PERIOD = 10;//should be %2 |
// Inputs |
reg nReset; |
reg clk; |
reg [15:0] clkPerCycle; |
reg startActivation; |
reg startDeactivation; |
reg [7:0] dataIn; |
reg nWeDataIn; |
reg [12:0] cyclePerEtu; |
reg nCsDataOut; |
reg nCsStatusOut; |
|
// Outputs |
wire [7:0] dataOut; |
wire [7:0] statusOut; |
wire isActivated; |
wire useIndirectConvention; |
wire tsError; |
wire tsReceived; |
wire atrIsEarly; |
wire atrIsLate; |
wire isoClk; |
wire isoReset; |
wire isoVdd; |
|
// Bidirs |
wire isoSio; |
|
// Instantiate the Unit Under Test (UUT) |
Iso7816_3_Master uut ( |
.nReset(nReset), |
.clk(clk), |
.clkPerCycle(clkPerCycle), |
.startActivation(startActivation), |
.startDeactivation(startDeactivation), |
.dataIn(dataIn), |
.nWeDataIn(nWeDataIn), |
.cyclePerEtu(cyclePerEtu), |
.dataOut(dataOut), |
.nCsDataOut(nCsDataOut), |
.statusOut(statusOut), |
.nCsStatusOut(nCsStatusOut), |
.isActivated(isActivated), |
.useIndirectConvention(useIndirectConvention), |
.tsError(tsError), |
.tsReceived(tsReceived), |
.atrIsEarly(atrIsEarly), |
.atrIsLate(atrIsLate), |
.isoSio(isoSio), |
.isoClk(isoClk), |
.isoReset(isoReset), |
.isoVdd(isoVdd) |
); |
|
DummyCard card( |
.isoReset(isoReset), |
.isoClk(isoClk), |
.isoVdd(isoVdd), |
.isoSio(isoSio) |
); |
integer tbErrorCnt; |
initial begin |
// Initialize Inputs |
nReset = 0; |
clk = 0; |
clkPerCycle = 0; |
startActivation = 0; |
startDeactivation = 0; |
dataIn = 0; |
nWeDataIn = 0; |
cyclePerEtu = 0; |
nCsDataOut = 0; |
nCsStatusOut = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
nReset = 1; |
// Add stimulus here |
#100 |
startActivation = 1'b1; |
wait(isActivated); |
wait(atrIsEarly|atrIsLate); |
#200 |
$finish; |
end |
initial begin |
// timeout |
#10000; |
tbErrorCnt=tbErrorCnt+1; |
$display("ERROR: timeout expired"); |
#10; |
$finish; |
end |
always |
#(CLK_PERIOD/2) clk = ! clk; |
endmodule |
|
/TxCoreTestBench.v
6,7 → 6,7
// |
// Create Date: 22:53:00 08/29/2010 |
// Design Name: TxCore |
// Module Name: D:/Hardware/Uart/tb_TxCore.v |
// Module Name: tb_TxCore.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
/DummyCard.v
0,0 → 1,96
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 22:22:43 01/10/2011 |
// Design Name: HalfDuplexUartIf |
// Module Name: dummyCard.v |
// Project Name: Uart |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module DummyCard( |
input isoReset, |
input isoClk, |
input isoVdd, |
inout isoSio |
); |
|
// Inputs |
wire [0:0] clkPerCycle=0; |
reg [7:0] dataIn; |
reg nWeDataIn; |
reg nCsDataOut; |
reg nCsStatusOut; |
|
// Outputs |
wire [7:0] dataOut; |
wire [7:0] statusOut; |
wire serialOut; |
|
|
|
// Instantiate the Unit Under Test (UUT) |
HalfDuplexUartIf uut ( |
.nReset(isoReset), |
.clk(isoClk), |
.clkPerCycle(clkPerCycle), |
.dataIn(dataIn), |
.nWeDataIn(nWeDataIn), |
.dataOut(dataOut), |
.nCsDataOut(nCsDataOut), |
.statusOut(statusOut), |
.nCsStatusOut(nCsStatusOut), |
.serialIn(isoSio), |
.serialOut(serialOut), |
.comClk(comClk) |
); |
|
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull; |
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut; |
|
assign isoSio = isTx ? serialOut : 1'bz; |
|
reg sendAtr; |
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release |
always @(posedge isoClk, negedge isoReset) begin |
if(~isoReset) begin |
nWeDataIn<=1'b1; |
nCsDataOut<=1'b1; |
nCsStatusOut<=1'b1; |
|
tsCnt<=9'b0; |
sendAtr<=1'b1; |
end else if(tsCnt!=9'd400) begin |
tsCnt <= tsCnt + 1'b1; |
end else if(sendAtr) begin |
sendAtr<=1'b0; |
dataIn<=8'h3B; |
nWeDataIn<=1'b0; |
@(posedge isoClk) |
nWeDataIn<=1'b1; |
@(posedge isoClk)//should not be needed |
wait(txPending==0); |
dataIn<=8'h00; |
nWeDataIn<=1'b0; |
@(posedge isoClk) |
nWeDataIn<=1'b1; |
end else begin |
end |
end |
|
endmodule |
|