OpenCores
URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /iso7816_3_master/trunk/test
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/ComDriverTasks.v
0,0 → 1,62
 
//wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
//assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = COM_statusOut;
 
 
task sendByte;
input [7:0] data;
begin
wait(bufferFull==1'b0);
dataIn=data;
nWeDataIn=0;
@(posedge COM_clk);
dataIn=8'hxx;
nWeDataIn=1;
@(posedge COM_clk);
end
endtask
task sendWord;
input [15:0] data;
begin
sendByte(data[15:8]);
sendByte(data[7:0]);
end
endtask
task waitEndOfTx;
begin
@(posedge COM_clk)
wait(txPending==0);
wait(isTx==0);
end
endtask
task privateTaskReceiveByteCore;
begin
wait(txPending==1'b0);//wait start of last tx if any
wait(txRun==1'b0);//wait end of previous transmission if any
wait(bufferFull==1'b1);//wait reception of a byte
@(posedge COM_clk);
nCsDataOut=0;
@(posedge COM_clk);
nCsDataOut=1;
end
endtask
task receiveByte;
output reg [7:0] rxData;
begin
privateTaskReceiveByteCore;
rxData=dataOut;
@(posedge COM_clk);
end
endtask
task receiveAndCheckByte;
input [7:0] data;
begin
privateTaskReceiveByteCore;
if(data!=dataOut) begin
COM_errorCnt=COM_errorCnt+1;
$display("ERROR %d: Received %x instead of %x",COM_errorCnt, dataOut, data);
end
@(posedge COM_clk);
end
endtask
 
/tbIso7816_3_Master.v
1,5 → 1,5
`timescale 1ns / 1ps
 
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
52,6 → 52,15
// Bidirs
wire isoSio;
 
wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
 
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
 
`include "ComDriverTasks.v"
 
// Instantiate the Unit Under Test (UUT)
Iso7816_3_Master uut (
.nReset(nReset),
84,9 → 93,11
.isoVdd(isoVdd),
.isoSio(isoSio)
);
integer tbErrorCnt;
initial begin
// Initialize Inputs
COM_errorCnt=0;
nReset = 0;
clk = 0;
clkPerCycle = 0;
93,10 → 104,10
startActivation = 0;
startDeactivation = 0;
dataIn = 0;
nWeDataIn = 0;
nWeDataIn = 1'b1;
cyclePerEtu = 0;
nCsDataOut = 0;
nCsStatusOut = 0;
nCsDataOut = 1'b1;
nCsStatusOut = 1'b1;
 
// Wait 100 ns for global reset to finish
#100;
105,13 → 116,45
#100
startActivation = 1'b1;
wait(isActivated);
wait(atrIsEarly|atrIsLate);
wait(tsReceived);
if(atrIsEarly) begin
$display("ERROR: ATR is early");
tbErrorCnt=tbErrorCnt+1;
end
if(atrIsLate) begin
$display("ERROR: ATR is late");
tbErrorCnt=tbErrorCnt+1;
end
@(posedge clk);
while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
@(posedge clk);
end
@(posedge clk);
end
$display("Two cycle pause in communication detected, stop simulation");
#200
$finish;
end
//T=0 tpdu stimuli
initial begin
receiveAndCheckByte(8'h3B);
receiveAndCheckByte(8'h00);
//sendBytes("000C000001");//would be handy, TODO
sendByte(8'h00);
sendByte(8'h0C);
sendByte(8'h00);
sendByte(8'h00);
sendByte(8'h01);
receiveAndCheckByte(8'h0C);
//sendBytes("55");
sendByte(8'h55);
receiveAndCheckByte(8'h90);
receiveAndCheckByte(8'h00);
end
initial begin
// timeout
#10000;
#100000;
tbErrorCnt=tbErrorCnt+1;
$display("ERROR: timeout expired");
#10;
/DummyCard.v
1,5 → 1,5
`timescale 1ns / 1ps
 
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
23,10 → 23,10
////////////////////////////////////////////////////////////////////////////////
 
module DummyCard(
input isoReset,
input isoClk,
input isoVdd,
inout isoSio
input wire isoReset,
input wire isoClk,
input wire isoVdd,
inout wire isoSio
);
 
// Inputs
42,9 → 42,8
wire serialOut;
 
 
// Instantiate the Unit Under Test (UUT)
HalfDuplexUartIf uut (
wire cardIsoClk;//card use its own generated clock (like true UARTs)
HalfDuplexUartIf uartIf (
.nReset(isoReset),
.clk(isoClk),
.clkPerCycle(clkPerCycle),
56,22 → 55,83
.nCsStatusOut(nCsStatusOut),
.serialIn(isoSio),
.serialOut(serialOut),
.comClk(comClk)
.comClk(cardIsoClk)
);
 
reg sendAtr;
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
reg [7:0] buffer[256+5:0];
localparam CLA_I= 8*4;
localparam INS_I= 8*3;
localparam P1_I = 8*2;
localparam P2_I = 8*1;
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
 
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
 
`include "ComDriverTasks.v"
 
assign isoSio = isTx ? serialOut : 1'bz;
 
reg sendAtr;
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
/*T=0 card model
 
ATR:
3B 00
 
Implemented commands:
write buffer:
tpdu: 00 0C 00 00 LC data
sw: 90 00
read buffer:
tpdu: 00 0A 00 00 LE
response: data
sw: 90 00
any other:
sw: 69 86
*/
task sendAckByte;
sendByte(tpduHeader[INS_I+7:INS_I]);
endtask
 
task writeBufferCmd;
integer i;
begin
sendAckByte;
for(i=0;i<tpduHeader[P3_I+7:P3_I];i=i+1) begin
receiveByte(buffer[i]);
end
sendWord(16'h9000);
end
endtask
 
task readBufferCmd;
integer i;
integer le;
begin
sendAckByte;
le=tpduHeader[P3_I+7:P3_I];
if(0==le) le=256;
for(i=0;i<le;i=i+1) begin
sendByte(buffer[i]);
end
sendWord(16'h9000);
end
endtask
 
integer i;
always @(posedge isoClk, negedge isoReset) begin
if(~isoReset) begin
nWeDataIn<=1'b1;
nCsDataOut<=1'b1;
nCsStatusOut<=1'b1;
tsCnt<=9'b0;
sendAtr<=1'b1;
end else if(tsCnt!=9'd400) begin
78,17 → 138,19
tsCnt <= tsCnt + 1'b1;
end else if(sendAtr) begin
sendAtr<=1'b0;
dataIn<=8'h3B;
nWeDataIn<=1'b0;
@(posedge isoClk)
nWeDataIn<=1'b1;
@(posedge isoClk)//should not be needed
wait(txPending==0);
dataIn<=8'h00;
nWeDataIn<=1'b0;
@(posedge isoClk)
nWeDataIn<=1'b1;
sendByte(8'h3B);
sendByte(8'h00);
waitEndOfTx;
end else begin
//get tpdu
for(i=0;i<5;i=i+1)
receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
//dispatch
case(tpduHeader[7+CLA_I:P2_I])
32'h000C0000: writeBufferCmd;
32'h000A0000: readBufferCmd;
default: sendWord(16'h6986);
endcase
end
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.