URL
https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
Subversion Repositories iso7816_3_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/iso7816_3_master/trunk/test
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/tsAnalyzer.v
3,7 → 3,6
|
module TsAnalyzer( |
input wire nReset, |
input wire clk, |
input wire isoReset, |
input wire isoClk, |
input wire isoVdd, |
10,12 → 9,12
input wire isoSio, |
input wire endOfRx, |
input wire [7:0] rxData,//assumed to be sent lsb first, high level coding logical 1. |
output reg isActivated, |
output reg tsReceived, |
output reg tsError, |
output reg atrIsEarly,//high if TS received before 400 cycles after reset release |
output reg atrIsLate,//high if TS is still not received after 40000 cycles after reset release |
output reg useIndirectConvention |
output wire isActivated, |
output wire tsReceived, |
output wire tsError, |
output wire atrIsEarly,//high if TS received before 400 cycles after reset release |
output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release |
output wire useIndirectConvention |
); |
|
|
29,16 → 28,18
assign atrIsLate = resetCnt>(16'h100+16'd40000); |
assign useIndirectConvention = ~waitTs & (ts==8'hFC);//FC is 3F written LSB first |
assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention; |
always @(posedge comClk, negedge nReset) begin |
|
assign isActivated = isoReset & isoVdd; |
|
always @(posedge isoClk, negedge nReset) begin |
if(~nReset) begin |
resetCnt<=16'b0; |
waitTs<=1'b1; |
isActivated <= 1'b0; |
end else if(isActivated) begin |
if(waitTs) begin |
if(endOfRx) begin |
waitTs<=1'b0; |
ts<=dataOut; |
ts<=rxData; |
end |
resetCnt<=resetCnt+1; |
end |
/FiDiAnalyzer.v
5,12 → 5,12
input wire [3:0] fiCode, |
input wire [3:0] diCode, |
output wire [12:0] fi, |
output wire [7:0] di, |
output wire [12:0] cyclesPerEtu, //truncate values to 'floor' integer value |
output reg [7:0] di, |
output reg [12:0] cyclesPerEtu, //truncate values to 'floor' integer value |
output wire [7:0] fMax //in 0.1MHz units |
); |
|
wire [13+8] fiStuff; |
reg [13+8:0] fiStuff; |
assign {fi,fMax} = fiStuff; |
always @(*) begin:fiBlock |
case(fiCode) |
/tbIso7816_3_Master.v
61,6 → 61,21
|
`include "ComDriverTasks.v" |
|
|
wire [3:0] spy_fiCode; |
wire [3:0] spy_diCode; |
wire [12:0] spy_fi; |
wire [7:0] spy_di; |
wire [12:0] spy_cyclesPerEtu; |
wire [7:0] spy_fMax; |
wire spy_isActivated,spy_tsReceived,spy_tsError; |
wire spy_useIndirectConvention,spy_atrIsEarly,spy_atrIsLate; |
wire [3:0] spy_atrK; |
wire spy_atrHasTck,spy_atrCompleted; |
wire spy_useT0,spy_useT1,spy_useT15,spy_waitCardTx,spy_waitTermTx,spy_cardTx,spy_termTx,spy_guardTime; |
wire spy_overrunError,spy_frameError; |
wire [7:0] spy_lastByte; |
|
// Instantiate the Unit Under Test (UUT) |
Iso7816_3_Master uut ( |
.nReset(nReset), |
93,6 → 108,43
.isoVdd(isoVdd), |
.isoSio(isoSio) |
); |
|
Iso7816_3_t0_analyzer spy ( |
.nReset(nReset), |
.clk(clk), |
.clkPerCycle(clkPerCycle[0]), |
.isoReset(isoReset), |
.isoClk(isoClk), |
.isoVdd(isoVdd), |
.isoSio(isoSio), |
.fiCode(spy_fiCode), |
.diCode(spy_diCode), |
.fi(spy_fi), |
.di(spy_di), |
.cyclesPerEtu(spy_cyclesPerEtu), |
.fMax(spy_fMax), |
.isActivated(spy_isActivated), |
.tsReceived(spy_tsReceived), |
.tsError(spy_tsError), |
.useIndirectConvention(spy_useIndirectConvention), |
.atrIsEarly(spy_atrIsEarly), |
.atrIsLate(spy_atrIsLate), |
.atrK(spy_atrK), |
.atrHasTck(spy_atrHasTck), |
.atrCompleted(spy_atrCompleted), |
.useT0(spy_useT0), |
.useT1(spy_useT1), |
.useT15(spy_useT15), |
.waitCardTx(spy_waitCardTx), |
.waitTermTx(spy_waitTermTx), |
.cardTx(spy_cardTx), |
.termTx(spy_termTx), |
.guardTime(spy_guardTime), |
.overrunError(spy_overrunError), |
.frameError(spy_frameError), |
.lastByte(spy_lastByte) |
); |
|
|
integer tbErrorCnt; |
initial begin |
/HammingWeight.v
0,0 → 1,54
|
`timescale 1ns / 1ps |
`default_nettype none |
|
module HammingWeight( |
dataIn, |
hammingWeight |
); |
parameter DATA_WIDTH=4; |
parameter WEIGHT_WIDTH=2; |
|
input wire [DATA_WIDTH-1:0] dataIn; |
output reg [WEIGHT_WIDTH-1:0] hammingWeight; |
|
always @(*) begin:hamminWeightBlock |
integer i; |
for(i=0;i<DATA_WIDTH;i=i+1) begin |
hammingWeight=hammingWeight + dataIn[i]; |
end |
end |
endmodule |
|
/* |
task hammingWeight |
parameter DATA_WIDTH=4; |
parameter WEIGHT_WIDTH=2; |
input wire [DATA_WIDTH-1:0] dataIn; |
output reg [WEIGHT_WIDTH-1:0] hammingWeight; |
integer i; |
begin |
|
for(i=0;i<DATA_WIDTH;i=i+1) begin |
hammingWeight=hammingWeight + dataIn[i]; |
end |
|
end |
endtask |
*/ |
/* |
function hammingWeight |
parameter DATA_WIDTH=4; |
parameter WEIGHT_WIDTH=2; |
input wire [DATA_WIDTH-1:0] dataIn; |
output reg [WEIGHT_WIDTH-1:0] hammingWeight; |
integer i; |
begin |
|
for(i=0;i<DATA_WIDTH;i=i+1) begin |
hammingWeight=hammingWeight + dataIn[i]; |
end |
|
end |
endtask |
*/ |
/iso7816_3_t0_analyzer.v
4,6 → 4,7
module Iso7816_3_t0_analyzer( |
input wire nReset, |
input wire clk, |
input wire [DIVIDER_WIDTH-1:0] clkPerCycle, |
input wire isoReset, |
input wire isoClk, |
input wire isoVdd, |
10,10 → 11,10
input wire isoSio, |
output reg [3:0] fiCode, |
output reg [3:0] diCode, |
output reg [3:0] fi, |
output reg [3:0] di, |
output reg [12:0] cyclesPerEtu, |
output reg [7:0] fMax, |
output wire [12:0] fi, |
output wire [7:0] di, |
output wire [12:0] cyclesPerEtu, |
output wire [7:0] fMax, |
output wire isActivated, |
output wire tsReceived, |
output wire tsError, |
20,20 → 21,22
output wire useIndirectConvention, |
output wire atrIsEarly,//high if TS received before 400 cycles after reset release |
output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release |
output wire atrCompleted, |
output reg [3:0] atrK,//number of historical bytes |
output reg atrHasTck, |
output reg atrCompleted, |
output reg useT0, |
output reg useT1, |
output reg useT15, |
output reg waitCardTx, |
output reg waitTermTx, |
output wire cardTx, |
output wire termTx, |
output reg cardTx, |
output reg termTx, |
output wire guardTime, |
output wire overrunError, |
output wire frameError, |
output reg [7:0] lastByte |
); |
|
parameter DIVIDER_WIDTH = 1; |
|
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release |
|
45,9 → 48,11
localparam P3_I = 0; |
reg [CLA_I+7:0] tpduHeader; |
|
wire COM_statusOut=statusOut; |
//wire COM_statusOut=statusOut; |
wire COM_clk=isoClk; |
integer COM_errorCnt; |
wire txPending=1'b0; |
wire txRun=1'b0; |
|
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull; |
assign overrunErrorFlag = overrunError; |
54,20 → 59,24
assign frameErrorFlag = frameError; |
|
wire [7:0] rxData; |
wire nCsDataOut; |
reg nCsDataOut; |
|
wire msbFirst = useIndirectConvention; |
wire sioHighValue = ~useIndirectConvention; |
wire oddParity = 1'b0; |
|
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData; |
|
|
`include "ComRxDriverTasks.v" |
|
wire endOfRx; |
|
wire msbFirst = useIndirectConvention; |
wire sioHighValue = ~useIndirectConvention; |
wire oddParity = 1'b0; |
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte |
|
wire plainRxData = sioHighValue ? rxData : ~rxData; |
|
RxCoreSelfContained #( |
.DIVIDER_WIDTH(4'd13)) |
.DIVIDER_WIDTH(DIVIDER_WIDTH), |
.CLOCK_PER_BIT_WIDTH(4'd13)) |
rxCore ( |
.dataOut(rxData), |
.overrunErrorFlag(overrunError), |
84,7 → 93,7
.msbFirst(msbFirst), |
.ackFlags(nCsDataOut), |
.serialIn(isoSio), |
.comClk(comClk), |
.comClk(isoClk), |
.clk(clk), |
.nReset(nReset) |
); |
91,7 → 100,6
|
TsAnalyzer tsAnalyzer( |
.nReset(nReset), |
.clk(clk), |
.isoReset(isoReset), |
.isoClk(isoClk), |
.isoVdd(isoVdd), |
116,24 → 124,82
); |
|
wire run = rxStartBit | rxRun; |
localparam WAIT_CLA = 0; |
integer t0State; |
always @(posedge comClk, negedge nReset) begin |
localparam ATR_T0 = 0; |
localparam ATR_TDI = 1; |
localparam ATR_HISTORICAL = 2; |
localparam ATR_TCK = 3; |
localparam T0_HEADER = 0; |
localparam T0_PB = 0; |
localparam T0_DATA = 0; |
integer fsmState; |
|
reg [11:0] tdiStruct; |
wire [3:0] tdiCnt;//i+1 |
wire [7:0] tdiData;//value of TDi |
assign {tdiCnt,tdiData}=tdiStruct; |
|
wire [1:0] nIfBytes; |
HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes)); |
reg [7:0] bytesCnt; |
|
always @(posedge isoClk, negedge nReset) begin |
if(~nReset) begin |
fiCode<=4'b0001; |
diCode<=4'b0001; |
useT0<=1'b0; |
useT0<=1'b1; |
useT1<=1'b0; |
useT15<=1'b0; |
waitCardTx<=1'b0; |
waitTermTx<=1'b0; |
lastByte<=8'b0; |
t0State<=WAIT_CLA; |
fsmState<=ATR_TDI; |
atrHasTck<=1'b0; |
bytesCnt<=8'h0; |
tdiStruct<=12'h0; |
atrCompleted<=1'b0; |
end else if(isActivated) begin |
if(~tsReceived) begin |
waitCardTx<=1'b1; |
end else if(~t0Received) begin |
end else if(~atrCompleted) begin |
//ATR analysis |
case(fsmState) |
ATR_TDI: begin |
if(endOfRx) begin |
if(bytesCnt==nIfBytes) begin //TDi bytes |
bytesCnt <= 2'h0; |
tdiStruct <= {tdiCnt+1,dataOut}; |
if(4'h0==tdiCnt) begin//this is T0 |
atrK <= dataOut[3:0]; |
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI : |
(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER; |
end else begin//TDi, i from 1 to 15 |
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI : |
(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER; |
end |
end else begin //TA, TB or TC bytes |
//TODO: get relevant info |
bytesCnt <= bytesCnt+1; |
end |
end |
end |
ATR_HISTORICAL: begin |
if(endOfRx) begin |
if(bytesCnt==atrK) begin |
atrCompleted <= ~atrHasTck; |
fsmState <= atrHasTck ? ATR_TCK : T0_HEADER; |
end else begin |
bytesCnt <= bytesCnt+1; |
end |
end |
end |
ATR_TCK: begin |
if(endOfRx) begin |
//TODO:check |
atrCompleted <= 1'b1; |
fsmState <= T0_HEADER; |
end |
end |
endcase |
end else if(useT0) begin |
//T=0 cmd/response monitoring state machine |
|
144,16 → 210,16
|
reg [1:0] txDir; |
always @(*) begin: errorSigDirectionBlock |
if(stopBit & ~isoSio) |
{cardTx, termTx}=txDir[0:1]; |
if(guardTime & ~isoSio) |
{cardTx, termTx}={txDir[0],txDir[1]}; |
else |
{cardTx, termTx}=txDir[1:0]; |
{cardTx, termTx}={txDir[1],txDir[0]}; |
end |
always @(posedge comClk, negedge nReset) begin: comDirectionBlock |
always @(posedge isoClk, negedge nReset) begin: comDirectionBlock |
if(~nReset | ~run) begin |
txDir<=2'b00; |
end else begin |
if(~stopBit) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here |
if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here |
case({waitCardTx, waitTermTx}) |
2'b00: txDir<=2'b00; |
2'b01: txDir<=2'b01; |