OpenCores
URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /iso7816_3_master/trunk/test
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/tbIso7816_3_Master.v
32,7 → 32,7
reg startDeactivation;
reg [7:0] dataIn;
reg nWeDataIn;
reg [12:0] cyclePerEtu;
reg [12:0] cyclesPerEtu;
reg nCsDataOut;
reg nCsStatusOut;
 
75,6 → 75,7
wire spy_useT0,spy_useT1,spy_useT15,spy_waitCardTx,spy_waitTermTx,spy_cardTx,spy_termTx,spy_guardTime;
wire spy_overrunError,spy_frameError;
wire [7:0] spy_lastByte;
wire [31:0] spy_bytesCnt;
 
// Instantiate the Unit Under Test (UUT)
Iso7816_3_Master uut (
85,7 → 86,7
.startDeactivation(startDeactivation),
.dataIn(dataIn),
.nWeDataIn(nWeDataIn),
.cyclePerEtu(cyclePerEtu),
.cyclesPerEtu(cyclesPerEtu),
.dataOut(dataOut),
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
142,7 → 143,8
.guardTime(spy_guardTime),
.overrunError(spy_overrunError),
.frameError(spy_frameError),
.lastByte(spy_lastByte)
.lastByte(spy_lastByte),
.bytesCnt(spy_bytesCnt)
);
 
157,7 → 159,7
startDeactivation = 0;
dataIn = 0;
nWeDataIn = 1'b1;
cyclePerEtu = 0;
cyclesPerEtu = 372-1;
nCsDataOut = 1'b1;
nCsStatusOut = 1'b1;
 
206,7 → 208,7
end
initial begin
// timeout
#100000;
#10000000;
tbErrorCnt=tbErrorCnt+1;
$display("ERROR: timeout expired");
#10;
/DummyCard.v
40,7 → 40,7
wire [7:0] dataOut;
wire [7:0] statusOut;
wire serialOut;
reg [12:0] cyclesPerEtu;
 
wire cardIsoClk;//card use its own generated clock (like true UARTs)
HalfDuplexUartIf uartIf (
49,6 → 49,7
.clkPerCycle(clkPerCycle),
.dataIn(dataIn),
.nWeDataIn(nWeDataIn),
.clocksPerBit(cyclesPerEtu),
.dataOut(dataOut),
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
134,6 → 135,7
nCsStatusOut<=1'b1;
tsCnt<=9'b0;
sendAtr<=1'b1;
cyclesPerEtu <= 13'd372-1'b1;
end else if(tsCnt!=9'd400) begin
tsCnt <= tsCnt + 1'b1;
end else if(sendAtr) begin
/iso7816_3_t0_analyzer.v
34,7 → 34,8
output wire guardTime,
output wire overrunError,
output wire frameError,
output reg [7:0] lastByte
output reg [7:0] lastByte,
output reg [31:0] bytesCnt
);
parameter DIVIDER_WIDTH = 1;
48,11 → 49,10
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
//wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
wire txPending=1'b0;
wire txRun=1'b0;
//wire COM_clk=isoClk;
//integer COM_errorCnt;
//wire txPending=1'b0;
//wire txRun=1'b0;
 
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
assign overrunErrorFlag = overrunError;
59,7 → 59,7
assign frameErrorFlag = frameError;
 
wire [7:0] rxData;
reg nCsDataOut;
reg ackFlags;
 
wire msbFirst = useIndirectConvention;
wire sioHighValue = ~useIndirectConvention;
68,7 → 68,7
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
 
 
`include "ComRxDriverTasks.v"
//`include "ComRxDriverTasks.v"
 
wire endOfRx;
 
76,7 → 76,8
 
RxCoreSelfContained #(
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(4'd13))
.CLOCK_PER_BIT_WIDTH(4'd13),
.PRECISE_STOP_BIT(1'b1))
rxCore (
.dataOut(rxData),
.overrunErrorFlag(overrunError),
87,11 → 88,11
.startBit(rxStartBit),
.stopBit(guardTime),
.clkPerCycle(clkPerCycle),
.clocksPerBit(cyclesPerEtu),
.clocksPerBit(cyclesPerEtu-1),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
.ackFlags(nCsDataOut),
.ackFlags(ackFlags),
.serialIn(isoSio),
.comClk(isoClk),
.clk(clk),
140,10 → 141,22
 
wire [1:0] nIfBytes;
HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
reg [7:0] bytesCnt;
 
reg [7:0] tempBytesCnt;
always @(posedge isoClk, negedge nReset) begin
if(~nReset) begin
lastByte<=8'b0;
ackFlags<=1'b0;
bytesCnt<=32'b0;
end else if(ackFlags) begin
ackFlags<=1'b0;
end else if(frameErrorFlag|bufferFull) begin
lastByte<=dataOut;
ackFlags<=1'b1;
bytesCnt<=bytesCnt+1'b1;
end
end
always @(posedge isoClk, negedge nReset) begin
if(~nReset) begin
fiCode<=4'b0001;
diCode<=4'b0001;
useT0<=1'b1;
151,10 → 164,9
useT15<=1'b0;
waitCardTx<=1'b0;
waitTermTx<=1'b0;
lastByte<=8'b0;
fsmState<=ATR_TDI;
atrHasTck<=1'b0;
bytesCnt<=8'h0;
tempBytesCnt<=8'h0;
tdiStruct<=12'h0;
atrCompleted<=1'b0;
end else if(isActivated) begin
165,8 → 177,8
case(fsmState)
ATR_TDI: begin
if(endOfRx) begin
if(bytesCnt==nIfBytes) begin //TDi bytes
bytesCnt <= 2'h0;
if(tempBytesCnt==nIfBytes) begin //TDi bytes
tempBytesCnt <= 2'h0;
tdiStruct <= {tdiCnt+1,dataOut};
if(4'h0==tdiCnt) begin//this is T0
atrK <= dataOut[3:0];
178,17 → 190,17
end
end else begin //TA, TB or TC bytes
//TODO: get relevant info
bytesCnt <= bytesCnt+1;
tempBytesCnt <= tempBytesCnt+1;
end
end
end
ATR_HISTORICAL: begin
if(endOfRx) begin
if(bytesCnt==atrK) begin
if(tempBytesCnt==atrK) begin
atrCompleted <= ~atrHasTck;
fsmState <= atrHasTck ? ATR_TCK : T0_HEADER;
end else begin
bytesCnt <= bytesCnt+1;
tempBytesCnt <= tempBytesCnt+1;
end
end
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.