URL
https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
Subversion Repositories iso7816_3_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/iso7816_3_master
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
trunk/test/ComTxDriverTasks.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/tb_BasicHalfDuplexUart.v
===================================================================
--- trunk/test/tb_BasicHalfDuplexUart.v (revision 9)
+++ trunk/test/tb_BasicHalfDuplexUart.v (revision 10)
trunk/test/tb_BasicHalfDuplexUart.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/FiDiAnalyzer.v
===================================================================
--- trunk/test/FiDiAnalyzer.v (revision 9)
+++ trunk/test/FiDiAnalyzer.v (revision 10)
trunk/test/FiDiAnalyzer.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/HexStringConversion.v
===================================================================
--- trunk/test/HexStringConversion.v (revision 9)
+++ trunk/test/HexStringConversion.v (revision 10)
trunk/test/HexStringConversion.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/DummyCard.v
===================================================================
--- trunk/test/DummyCard.v (revision 9)
+++ trunk/test/DummyCard.v (revision 10)
trunk/test/DummyCard.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/TriWire.v
===================================================================
--- trunk/test/TriWire.v (nonexistent)
+++ trunk/test/TriWire.v (revision 10)
@@ -0,0 +1,73 @@
+`timescale 1ns / 1ps
+`default_nettype none
+/*****************************************************************
+* module triwire: bidirectional wire bus model with delay
+*
+* This module models the two ends of a bidirectional bus with
+* transport (not inertial) delays in each direction. The
+* bus has a width of WIDTH and the delays are as follows:
+* a->b has a delay of Ta_b (in `timescale units)
+* b->a has a delay of Tb_a (in `timescale units)
+* The two delays will typically be the same. This model
+* overcomes the problem of "echoes" at the receiving end of the
+* wire by ensuring that data is only transmitted down the wire
+* when the received data is Z. That means that there may be
+* collisions resulting in X at the local end, but X's are not
+* transmitted to the other end, which is a limitation of the
+* model. Another compromise made in the interest of simulation
+* speed is that the bus is not treated as individual wires, so
+* a Z on any single wire may prevent data from being transmitted
+* on other wires.
+*
+* The delays are reals so that they may vary throughout the
+* course of a simulation. To change the delay, use the Verilog
+* force command. Here is an example instantiation template:
+*
+real Ta_b=1, Tb_a=1;
+always(Ta_b) force triwire.Ta_b = Ta_b;
+always(Tb_a) force triwire.Tb_a = Tb_a;
+triwire #(.WIDTH(WIDTH)) triwire (.a(a),.b(b));
+
+* Kevin Neilson, Xilinx, 2007
+*****************************************************************/
+module triwire #(parameter WIDTH=1) (inout wire [WIDTH-1:0] a, b);
+ real Ta_b=1, Tb_a=1;
+ reg [WIDTH-1:0] a_dly = 'bz, b_dly = 'bz;
+ always @(a) a_dly <= #(Ta_b) b_dly==={WIDTH{1'bz}} ? a : 'bz;
+ always @(b) b_dly <= #(Tb_a) a_dly==={WIDTH{1'bz}} ? b : 'bz;
+ assign b = a_dly, a = b_dly;
+endmodule
+
+//delay fixed at build time here
+//Sebastien Riou
+module TriWirePullup #(parameter UNIDELAY=1)
+ (inout wire a, b);
+ reg a_dly = 'bz, b_dly = 'bz;
+ always @(a) begin
+ if(b_dly!==1'b0) begin
+ if(a===1'b0)
+ a_dly <= #(UNIDELAY) 1'b0;
+ else
+ a_dly <= #(UNIDELAY) 1'bz;
+ end
+ end
+ always @(b) begin
+ if(a_dly!==1'b0) begin
+ if(b===1'b0)
+ b_dly <= #(UNIDELAY) 1'b0;
+ else
+ b_dly <= #(UNIDELAY) 1'bz;
+ end
+ end
+ assign b = a_dly, a = b_dly;
+ pullup(a);
+ pullup(b);
+endmodule
+/*module TriWireFixed #(parameter WIDTH=1)
+ (inout wire [WIDTH-1:0] a, b);
+ tran (a,b);//not supported by xilinx ISE, even just in simulation :-S
+ specify
+ (a*>b)=(1,1);
+ (b*>a)=(1,1);
+ endspecify
+endmodule */
trunk/test/TriWire.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/HammingWeight.v
===================================================================
--- trunk/test/HammingWeight.v (revision 9)
+++ trunk/test/HammingWeight.v (revision 10)
trunk/test/HammingWeight.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/tb_HalfDuplexUartIf.v
===================================================================
--- trunk/test/tb_HalfDuplexUartIf.v (revision 9)
+++ trunk/test/tb_HalfDuplexUartIf.v (revision 10)
trunk/test/tb_HalfDuplexUartIf.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/tsAnalyzer.v
===================================================================
--- trunk/test/tsAnalyzer.v (revision 9)
+++ trunk/test/tsAnalyzer.v (revision 10)
trunk/test/tsAnalyzer.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/ComDriverTasks.v
===================================================================
--- trunk/test/ComDriverTasks.v (revision 9)
+++ trunk/test/ComDriverTasks.v (revision 10)
trunk/test/ComDriverTasks.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/RxCoreTestBench.v
===================================================================
--- trunk/test/RxCoreTestBench.v (revision 9)
+++ trunk/test/RxCoreTestBench.v (revision 10)
trunk/test/RxCoreTestBench.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/tbIso7816_3_Master.v
===================================================================
--- trunk/test/tbIso7816_3_Master.v (revision 9)
+++ trunk/test/tbIso7816_3_Master.v (revision 10)
@@ -2,7 +2,7 @@
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
// Company:
-// Engineer:
+// Engineer: Sebastien Riou
//
// Create Date: 22:16:42 01/10/2011
// Design Name: Iso7816_3_Master
@@ -48,9 +48,14 @@
wire isoClk;
wire isoReset;
wire isoVdd;
+
+ //probe outputs
+ wire probe_termMon;
+ wire probe_cardMon;
// Bidirs
- wire isoSio;
+ wire isoSioTerm;
+ wire isoSioCard;
wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
@@ -97,7 +102,7 @@
.tsReceived(tsReceived),
.atrIsEarly(atrIsEarly),
.atrIsLate(atrIsLate),
- .isoSio(isoSio),
+ .isoSio(isoSioTerm),
.isoClk(isoClk),
.isoReset(isoReset),
.isoVdd(isoVdd)
@@ -107,8 +112,15 @@
.isoReset(isoReset),
.isoClk(isoClk),
.isoVdd(isoVdd),
- .isoSio(isoSio)
+ .isoSio(isoSioCard)
);
+
+ Iso7816_directionProbe probe(
+ .isoSioTerm(isoSioTerm),
+ .isoSioCard(isoSioCard),
+ .termMon(probe_termMon),
+ .cardMon(probe_cardMon)
+ );
Iso7816_3_t0_analyzer spy (
.nReset(nReset),
@@ -117,7 +129,9 @@
.isoReset(isoReset),
.isoClk(isoClk),
.isoVdd(isoVdd),
- .isoSio(isoSio),
+ .isoSioTerm(probe_termMon),
+ .isoSioCard(probe_cardMon),
+ .useDirectionProbe(1'b1),
.fiCode(spy_fiCode),
.diCode(spy_diCode),
.fi(spy_fi),
trunk/test/tbIso7816_3_Master.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/TxCoreTestBench.v
===================================================================
--- trunk/test/TxCoreTestBench.v (revision 9)
+++ trunk/test/TxCoreTestBench.v (revision 10)
trunk/test/TxCoreTestBench.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/Iso7816_directionProbe.v
===================================================================
--- trunk/test/Iso7816_directionProbe.v (nonexistent)
+++ trunk/test/Iso7816_directionProbe.v (revision 10)
@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+`default_nettype none
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer: Sebastien Riou
+//
+// Create Date: 17:14:04 01/29/2011
+// Design Name:
+// Module Name: Iso7816_directionProbe
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description: model a probe which consist only of wires. Propagation delay over the sio line
+// is used to determined the direction of the communication:
+// If the terminal send a start bit, the termMon output will go low before cardMon and viceversa
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Iso7816_directionProbe(
+ inout wire isoSioTerm,
+ inout wire isoSioCard,
+ output wire termMon,
+ output wire cardMon
+ );
+
+TriWirePullup sioLine(.a(isoSioTerm), .b(isoSioCard));
+assign termMon = isoSioTerm;
+assign cardMon = isoSioCard;
+
+endmodule
trunk/test/Iso7816_directionProbe.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/ComRxDriverTasks.v
===================================================================
--- trunk/test/ComRxDriverTasks.v (revision 9)
+++ trunk/test/ComRxDriverTasks.v (revision 10)
trunk/test/ComRxDriverTasks.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/test/iso7816_3_t0_analyzer.v
===================================================================
--- trunk/test/iso7816_3_t0_analyzer.v (revision 9)
+++ trunk/test/iso7816_3_t0_analyzer.v (revision 10)
@@ -1,7 +1,9 @@
`timescale 1ns / 1ps
`default_nettype none
-module Iso7816_3_t0_analyzer(
+module Iso7816_3_t0_analyzer
+#(parameter DIVIDER_WIDTH = 1)
+(
input wire nReset,
input wire clk,
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
@@ -8,7 +10,9 @@
input wire isoReset,
input wire isoClk,
input wire isoVdd,
- input wire isoSio,
+ input wire isoSioTerm,
+ input wire isoSioCard,
+ input wire useDirectionProbe,//if 1, isoSioTerm and isoSioCard must be connected to Iso7816_directionProbe outputs
output reg [3:0] fiCode,
output reg [3:0] diCode,
output wire [12:0] fi,
@@ -29,8 +33,8 @@
output reg useT15,
output reg waitCardTx,
output reg waitTermTx,
- output reg cardTx,
- output reg termTx,
+ output wire cardTx,
+ output wire termTx,
output wire guardTime,
output wire overrunError,
output wire frameError,
@@ -37,7 +41,8 @@
output reg [7:0] lastByte,
output reg [31:0] bytesCnt
);
-parameter DIVIDER_WIDTH = 1;
+
+wire isoSio = isoSioTerm & isoSioCard;
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
@@ -73,7 +78,7 @@
wire endOfRx;
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
-
+wire [12:0] clocksPerBit = cyclesPerEtu-1;
RxCoreSelfContained #(
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(4'd13),
@@ -88,7 +93,7 @@
.startBit(rxStartBit),
.stopBit(guardTime),
.clkPerCycle(clkPerCycle),
- .clocksPerBit(cyclesPerEtu-1),
+ .clocksPerBit(clocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
@@ -318,13 +323,15 @@
end
reg [1:0] txDir;
-always @(*) begin: errorSigDirectionBlock
+reg proto_cardTx;
+reg proto_termTx;
+always @(*) begin: protoComDirectionCombiBlock
if(guardTime & ~isoSio)
- {cardTx, termTx}={txDir[0],txDir[1]};
+ {proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
else
- {cardTx, termTx}={txDir[1],txDir[0]};
+ {proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
end
-always @(posedge isoClk, negedge nReset) begin: comDirectionBlock
+always @(posedge isoClk, negedge nReset) begin: protoComDirectionSeqBlock
if(~nReset | ~run) begin
txDir<=2'b00;
end else begin
@@ -338,6 +345,26 @@
end
end
end
+
+reg phy_cardTx;
+reg phy_termTx;
+always @(negedge isoSio, negedge nReset) begin: phyComDirectionBlock
+ if(~nReset) begin
+ phy_cardTx<=1'b0;
+ phy_termTx<=1'b0;
+ end else begin
+ if(~isoSioTerm) begin
+ phy_cardTx<=1'b0;
+ phy_termTx<=1'b1;
+ end else begin
+ phy_cardTx<=1'b1;
+ phy_termTx<=1'b0;
+ end
+ end
+end
+
+assign cardTx = useDirectionProbe ? phy_cardTx : proto_cardTx;
+assign termTx = useDirectionProbe ? phy_termTx : proto_termTx;
endmodule
trunk/test/iso7816_3_t0_analyzer.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/Uart.v
===================================================================
--- trunk/sources/Uart.v (revision 9)
+++ trunk/sources/Uart.v (revision 10)
trunk/sources/Uart.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/Iso7816_3_Master.v
===================================================================
--- trunk/sources/Iso7816_3_Master.v (revision 9)
+++ trunk/sources/Iso7816_3_Master.v (revision 10)
@@ -1,23 +1,14 @@
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 17:16:40 01/09/2011
-// Design Name:
-// Module Name: Iso7816_3_Master
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
+// Author: Sebastien Riou
+// Creation date: 17:16:40 01/09/2011
//
-// Dependencies:
+// Last change date: $LastChangedDate$
+// Last changed by: $LastChangedBy$
+// Last revision: $LastChangedRevision$
+// Head URL: $HeadURL$
//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
//////////////////////////////////////////////////////////////////////////////////
module Iso7816_3_Master(
input wire nReset,
trunk/sources/Iso7816_3_Master.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/RxCoreSpec.v
===================================================================
--- trunk/sources/RxCoreSpec.v (revision 9)
+++ trunk/sources/RxCoreSpec.v (revision 10)
trunk/sources/RxCoreSpec.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/Counter.v
===================================================================
--- trunk/sources/Counter.v (revision 9)
+++ trunk/sources/Counter.v (revision 10)
trunk/sources/Counter.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/ClkDivider.v
===================================================================
--- trunk/sources/ClkDivider.v (revision 9)
+++ trunk/sources/ClkDivider.v (revision 10)
trunk/sources/ClkDivider.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/RxCoreSelfContained.v
===================================================================
--- trunk/sources/RxCoreSelfContained.v (revision 9)
+++ trunk/sources/RxCoreSelfContained.v (revision 10)
trunk/sources/RxCoreSelfContained.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/RxCore.v
===================================================================
--- trunk/sources/RxCore.v (revision 9)
+++ trunk/sources/RxCore.v (revision 10)
trunk/sources/RxCore.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/TxCore.v
===================================================================
--- trunk/sources/TxCore.v (revision 9)
+++ trunk/sources/TxCore.v (revision 10)
trunk/sources/TxCore.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property
Index: trunk/sources/HalfDuplexUartIf.v
===================================================================
--- trunk/sources/HalfDuplexUartIf.v (revision 9)
+++ trunk/sources/HalfDuplexUartIf.v (revision 10)
trunk/sources/HalfDuplexUartIf.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Date Author Revision HeadURL
\ No newline at end of property