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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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    /iso7816_3_master
    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/trunk/test/ComTxDriverTasks.v
52,6 → 52,8
sendByte(data[7:0]);
end
endtask
 
//return when the stop bit of the last byte is starting
task waitEndOfTx;
begin
@(posedge COM_clk)
/trunk/test/FiDiAnalyzer.v
47,18 → 47,18
case(fiCode)
4'b0000: fiStuff = {12'd0372,8'd040};
4'b0001: fiStuff = {12'd0372,8'd050};
4'b0010: fiStuff = {12'd0372,8'd060};
4'b0011: fiStuff = {12'd0372,8'd080};
4'b0100: fiStuff = {12'd0372,8'd120};
4'b0101: fiStuff = {12'd0372,8'd160};
4'b0110: fiStuff = {12'd0372,8'd200};
4'b0010: fiStuff = {12'd0558,8'd060};
4'b0011: fiStuff = {12'd0744,8'd080};
4'b0100: fiStuff = {12'd1116,8'd120};
4'b0101: fiStuff = {12'd1488,8'd160};
4'b0110: fiStuff = {12'd1860,8'd200};
4'b0111: fiStuff = {12'd0000,8'd000};
4'b1000: fiStuff = {12'd0000,8'd000};
4'b1001: fiStuff = {12'd0372,8'd050};
4'b1010: fiStuff = {12'd0372,8'd075};
4'b1011: fiStuff = {12'd0372,8'd100};
4'b1100: fiStuff = {12'd0372,8'd150};
4'b1101: fiStuff = {12'd0372,8'd200};
4'b1001: fiStuff = {12'd0512,8'd050};
4'b1010: fiStuff = {12'd0768,8'd075};
4'b1011: fiStuff = {12'd1024,8'd100};
4'b1100: fiStuff = {12'd1536,8'd150};
4'b1101: fiStuff = {12'd2048,8'd200};
4'b1110: fiStuff = {12'd0000,8'd000};
4'b1111: fiStuff = {12'd0000,8'd000};
endcase
/trunk/test/DummyCard.v
161,8 → 161,8
if(8'hFF==tpduHeader[CLA_I+:8]) begin
//support only PPS8 for the time being
if(32'hFF789778==tpduHeader[7+CLA_I:P2_I]) begin
sendHexBytes("FF789778");
if(32'hFF109778==tpduHeader[7+CLA_I:P2_I]) begin
sendHexBytes("FF109778");
waitEndOfTx;
cyclesPerEtu <= 13'd8-1'b1;
end
/trunk/test/ComDriverTasks.v
33,4 → 33,10
`include "ComRxDriverTasks.v"
`include "ComTxDriverTasks.v"
 
task waitEndOfRun;
begin
@(posedge COM_clk)
wait((txRun|rxRun)==0);
end
endtask
 
/trunk/test/tbIso7816_3_Master.v
222,6 → 222,9
initial begin
tbTestSequenceDone=1'b0;
receiveAndCheckHexBytes("3B00");
sendHexBytes("FF109778");
receiveAndCheckHexBytes("FF109778");
cyclesPerEtu=8-1;
sendHexBytes("000C000001");
receiveAndCheckHexBytes("0C");
sendHexBytes("55");
/trunk/test/iso7816_3_t0_analyzer.v
84,7 → 84,10
localparam P2_I = 8*1;
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
localparam PPS0_I= CLA_I;
localparam PPS1_I= INS_I;
localparam PPS2_I= P1_I;
localparam PPS3_I= P2_I;
//wire COM_clk=isoClk;
//integer COM_errorCnt;
//wire txPending=1'b0;
102,10 → 105,6
wire oddParity = 1'b0;
 
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
 
 
//`include "ComRxDriverTasks.v"
 
wire endOfRx;
 
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
173,6 → 172,7
localparam T0_SW1 = 5;
localparam T0_SW2 = 6;
localparam T0_HEADER_PPS = 100;
localparam T0_PPS_RESPONSE = 101;
 
integer fsmState;
 
197,8 → 197,13
bytesCnt<=bytesCnt+1'b1;
end
end
reg ppsValidSoFar;
reg ppsAccepted;
wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
always @(posedge isoClk, negedge nReset) begin
if(~nReset) begin
ppsValidSoFar<=1'b0;
ppsAccepted<=1'b0;
fiCode<=4'b0001;
diCode<=4'b0001;
useT0<=1'b1;
273,11 → 278,61
tpduHeader[CLA_I+:8]<=dataOut;
tempBytesCnt <= 1;
if(8'hFF==dataOut)
fsmState <= T0_HEADER_PPS;//TODO
fsmState <= T0_HEADER_PPS;
else
fsmState <= T0_HEADER_TPDU;
end
end
T0_HEADER_PPS: begin
if(endOfRx) begin
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
if(3==tempBytesCnt) begin//support only 4 byte PPS
tempBytesCnt <= 8'h0;
fsmState <= T0_PPS_RESPONSE;
{waitCardTx,waitTermTx}<=2'b10;
ppsValidSoFar<=1'b1;
ppsAccepted<=1'b0;
end else begin
tempBytesCnt <= tempBytesCnt+1;
end
end
end
T0_PPS_RESPONSE: begin
if(3==tempBytesCnt) begin//support only 4 byte PPS
if(guardTime) begin
if(ppsValidSoFar & ppsDataMatch) begin
{fiCode,diCode}<=tpduHeader[PPS2_I+:8];
end
end
end
if(endOfRx) begin
ppsValidSoFar<=ppsValidSoFar & ppsDataMatch;
if(3==tempBytesCnt) begin//support only 4 byte PPS
tempBytesCnt <= 8'h0;
fsmState <= T0_HEADER;
{waitCardTx,waitTermTx}<=2'b01;
case(tpduHeader[(PPS1_I-(tempBytesCnt*8))+:8])
8'h11: begin
useT0<=1'b0;
useT1<=1'b1;
useT15<=1'b0;
end
8'h1F: begin
useT0<=1'b0;
useT1<=1'b0;
useT15<=1'b1;
end
default: begin
useT0<=1'b1;
useT1<=1'b0;
useT15<=1'b0;
end
endcase
end else begin
tempBytesCnt <= tempBytesCnt+1;
end
end
end
T0_HEADER_TPDU: begin
if(endOfRx) begin
tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
/trunk/sources/Uart.v
58,6 → 58,7
output wire rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
output wire txFull,
output wire isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
output wire endOfTx, //one cycle pulse: 1 during last cycle of last stop bit of tx
input wire serialIn, //signals to merged into a inout signal according to "isTx"
output wire serialOut,
75,42 → 76,21
input wire nReset
);
 
//constant definition for states
localparam IDLE_STATE = 3'b000;
localparam RX_STATE = 3'b001;
localparam TX_STATE = 3'b011;
 
wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
//wire serialOut;
wire loadDataIn;
 
wire txStopBits;
 
assign isTx = txRun & ~txStopBits;
//let this to top level to avoid inout signal
//assign serialLine = isTx ? serialOut : 1'bz;
 
assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
 
/*//complicated approach... instead we can simply divide the clock at lower levels
wire useEarlyComClk = |clkPerCycle ? 1'b1:1'b0;
reg dividedClk;
wire earlyComClk;//earlier than comClk by 1 cycle of clk (use to make 1 cycle pulse signals)
always @(posedge clk)begin
if(useEarlyComClk)
dividedClk <= earlyComClk;
reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
always @(posedge clk, negedge nReset) begin
if(~nReset) begin
safeClocksPerBit<=clocksPerBit;
end else if(endOfRx|endOfTx|~(rxRun|rxStartBit|txRun)) begin
safeClocksPerBit<=clocksPerBit;
end
end
assign comClk=useEarlyComClk ? dividedClk : clk;//clock for communication
wire endOfRxComClk;//pulse of 1 cycle of comClk
assign endOfRx = useEarlyComClk ? endOfRxComClk & earlyComClk & ~comClk : endOfRxComClk;//pulse of 1 cycle of clk
ClkDivider #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
clkDivider(
.nReset(nReset),
.clk(clk),
.divider(clkPerCycle),
.dividedClk(earlyComClk)
);
*/
 
wire stopBit;
// Instantiate the module
RxCoreSelfContained #(
127,7 → 107,7
.startBit(rxStartBit),
.stopBit(stopBit),
.clkPerCycle(clkPerCycle),
.clocksPerBit(clocksPerBit),
.clocksPerBit(safeClocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
142,12 → 122,13
)
txCore (
.serialOut(serialOut),
.run(txRun),
.run(txRun),
.endOfTx(endOfTx),
.full(txFull),
.stopBits(txStopBits),
.dataIn(txData),
.clkPerCycle(clkPerCycle),
.clocksPerBit(clocksPerBit),
.clocksPerBit(safeClocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
/trunk/sources/TxCore.v
43,7 → 43,8
(
output wire comClk,
output wire serialOut,
output wire run,
output wire run,
output reg endOfTx,
output wire full,
output wire stopBits, //1 during stop bits
input wire [7:0] dataIn,
142,7 → 143,8
always @(posedge clk, negedge nReset) begin
if(~nReset) begin
nextState <= #1 IDLE_STATE;
bitCounter <= #1 0;
bitCounter <= #1 0;
endOfTx <= #1 1'b0;
end else begin
case(nextState)
IDLE_STATE: begin
178,12 → 180,12
nextState <= #1 SEND_STOP2_STATE;
end
SEND_STOP2_STATE: begin
/* if(bitClocksCounter[1:0]==2'b10)
nextState <= #1 SEND_STOP2_STATE2;
end
SEND_STOP2_STATE2: begin*/
if(bitClocksCounterMatch)
if(bitClocksCounterEarlyMatch)
endOfTx <= #1 1'b1;
if(bitClocksCounterMatch) begin
nextState <= #1 IDLE_STATE;
endOfTx <= #1 1'b0;
end
end
default: nextState <= #1 IDLE_STATE;
endcase

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