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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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  • This comparison shows the changes necessary to convert path 
    /iso7816_3_master
    from Rev 12 to Rev 13
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  •

Rev 12 → Rev 13

/trunk/test/DummyCard.v
94,7 → 94,7
/*T=0 card model
 
ATR:
3B 00
3B/3F 94 97 80 1F 42 BA BE BA BE
 
Implemented commands:
write buffer:
149,7 → 149,10
tsCnt <= tsCnt + 1'b1;
end else if(sendAtr) begin
sendAtr<=1'b0;
sendHexBytes("3B00");
//sendHexBytes("3B00");
sendHexBytes("3B");
//sendHexBytes("3F");
sendHexBytes("9497801F42BABEBABE");
waitEndOfTx;
end else begin
//get CLA
/trunk/test/tbIso7816_3_Master.v
197,6 → 197,10
startActivation = 1'b1;
wait(isActivated);
wait(tsReceived);
if(tsError) begin
$display("ERROR: ATR's TS is invalid");
tbErrorCnt=tbErrorCnt+1;
end
if(atrIsEarly) begin
$display("ERROR: ATR is early");
tbErrorCnt=tbErrorCnt+1;
219,9 → 223,12
end
end
//T=0 tpdu stimuli
reg [7:0] byteFromCard;
initial begin
tbTestSequenceDone=1'b0;
receiveAndCheckHexBytes("3B00");
//receiveAndCheckHexBytes("3B00");
receiveByte(byteFromCard);//3B or 3F, so we don't check (Master and Spy do)
receiveAndCheckHexBytes("9497801F42BABEBABE");
sendHexBytes("FF109778");
receiveAndCheckHexBytes("FF109778");
cyclesPerEtu=8-1;
/trunk/test/iso7816_3_t0_analyzer.v
33,7 → 33,9
 
 
module Iso7816_3_t0_analyzer
#(parameter DIVIDER_WIDTH = 1)
#(
parameter DIVIDER_WIDTH = 1
)
(
input wire nReset,
input wire clk,
72,6 → 74,7
output reg [7:0] lastByte,
output reg [31:0] bytesCnt
);
localparam CLOCK_PER_BIT_WIDTH = 4'd13;
 
wire isoSio = isoSioTerm & isoSioCard;
108,10 → 111,20
wire endOfRx;
 
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
wire [12:0] clocksPerBit = cyclesPerEtu-1;
wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit = cyclesPerEtu-1;
 
reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
always @(posedge clk, negedge nReset) begin
if(~nReset) begin
safeClocksPerBit<=clocksPerBit;
end else if(endOfRx|~(rxRun|rxStartBit)) begin
safeClocksPerBit<=clocksPerBit;
end
end
 
RxCoreSelfContained #(
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(4'd13),
.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
.PRECISE_STOP_BIT(1'b1))
rxCore (
.dataOut(rxData),
123,7 → 136,7
.startBit(rxStartBit),
.stopBit(guardTime),
.clkPerCycle(clkPerCycle),
.clocksPerBit(clocksPerBit),
.clocksPerBit(safeClocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
241,18 → 254,24
end
end else begin //TA, TB or TC bytes
//TODO: get relevant info
tempBytesCnt <= tempBytesCnt+1;
//check if we just received the last interface byte
if((tempBytesCnt+1==nIfBytes) & (1'b0==tdiStruct[7])) begin
tempBytesCnt <= 2'h0;
fsmState <= (4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
end else begin
tempBytesCnt <= tempBytesCnt+1;
end
end
end
end
ATR_HISTORICAL: begin
if(endOfRx) begin
if(tempBytesCnt==atrK) begin
if(tempBytesCnt==(atrK-1)) begin
tempBytesCnt <= 8'h0;
if(atrHasTck) begin
fsmState <= ATR_TCK;
end else begin
atrCompleted <= ~atrHasTck;
atrCompleted <= 1'b1;
{waitCardTx,waitTermTx}<=2'b10;
fsmState <= T0_HEADER;
end

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