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Subversion Repositories iso7816_3_master

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Rev 3 → Rev 4

/trunk/test/ComDriverTasks.v
0,0 → 1,62
 
//wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
//assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = COM_statusOut;
 
 
task sendByte;
input [7:0] data;
begin
wait(bufferFull==1'b0);
dataIn=data;
nWeDataIn=0;
@(posedge COM_clk);
dataIn=8'hxx;
nWeDataIn=1;
@(posedge COM_clk);
end
endtask
task sendWord;
input [15:0] data;
begin
sendByte(data[15:8]);
sendByte(data[7:0]);
end
endtask
task waitEndOfTx;
begin
@(posedge COM_clk)
wait(txPending==0);
wait(isTx==0);
end
endtask
task privateTaskReceiveByteCore;
begin
wait(txPending==1'b0);//wait start of last tx if any
wait(txRun==1'b0);//wait end of previous transmission if any
wait(bufferFull==1'b1);//wait reception of a byte
@(posedge COM_clk);
nCsDataOut=0;
@(posedge COM_clk);
nCsDataOut=1;
end
endtask
task receiveByte;
output reg [7:0] rxData;
begin
privateTaskReceiveByteCore;
rxData=dataOut;
@(posedge COM_clk);
end
endtask
task receiveAndCheckByte;
input [7:0] data;
begin
privateTaskReceiveByteCore;
if(data!=dataOut) begin
COM_errorCnt=COM_errorCnt+1;
$display("ERROR %d: Received %x instead of %x",COM_errorCnt, dataOut, data);
end
@(posedge COM_clk);
end
endtask
 
/trunk/test/tbIso7816_3_Master.v
1,5 → 1,5
`timescale 1ns / 1ps
 
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
52,6 → 52,15
// Bidirs
wire isoSio;
 
wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
 
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
 
`include "ComDriverTasks.v"
 
// Instantiate the Unit Under Test (UUT)
Iso7816_3_Master uut (
.nReset(nReset),
84,9 → 93,11
.isoVdd(isoVdd),
.isoSio(isoSio)
);
integer tbErrorCnt;
initial begin
// Initialize Inputs
COM_errorCnt=0;
nReset = 0;
clk = 0;
clkPerCycle = 0;
93,10 → 104,10
startActivation = 0;
startDeactivation = 0;
dataIn = 0;
nWeDataIn = 0;
nWeDataIn = 1'b1;
cyclePerEtu = 0;
nCsDataOut = 0;
nCsStatusOut = 0;
nCsDataOut = 1'b1;
nCsStatusOut = 1'b1;
 
// Wait 100 ns for global reset to finish
#100;
105,13 → 116,45
#100
startActivation = 1'b1;
wait(isActivated);
wait(atrIsEarly|atrIsLate);
wait(tsReceived);
if(atrIsEarly) begin
$display("ERROR: ATR is early");
tbErrorCnt=tbErrorCnt+1;
end
if(atrIsLate) begin
$display("ERROR: ATR is late");
tbErrorCnt=tbErrorCnt+1;
end
@(posedge clk);
while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
@(posedge clk);
end
@(posedge clk);
end
$display("Two cycle pause in communication detected, stop simulation");
#200
$finish;
end
//T=0 tpdu stimuli
initial begin
receiveAndCheckByte(8'h3B);
receiveAndCheckByte(8'h00);
//sendBytes("000C000001");//would be handy, TODO
sendByte(8'h00);
sendByte(8'h0C);
sendByte(8'h00);
sendByte(8'h00);
sendByte(8'h01);
receiveAndCheckByte(8'h0C);
//sendBytes("55");
sendByte(8'h55);
receiveAndCheckByte(8'h90);
receiveAndCheckByte(8'h00);
end
initial begin
// timeout
#10000;
#100000;
tbErrorCnt=tbErrorCnt+1;
$display("ERROR: timeout expired");
#10;
/trunk/test/DummyCard.v
1,5 → 1,5
`timescale 1ns / 1ps
 
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
23,10 → 23,10
////////////////////////////////////////////////////////////////////////////////
 
module DummyCard(
input isoReset,
input isoClk,
input isoVdd,
inout isoSio
input wire isoReset,
input wire isoClk,
input wire isoVdd,
inout wire isoSio
);
 
// Inputs
42,9 → 42,8
wire serialOut;
 
 
// Instantiate the Unit Under Test (UUT)
HalfDuplexUartIf uut (
wire cardIsoClk;//card use its own generated clock (like true UARTs)
HalfDuplexUartIf uartIf (
.nReset(isoReset),
.clk(isoClk),
.clkPerCycle(clkPerCycle),
56,22 → 55,83
.nCsStatusOut(nCsStatusOut),
.serialIn(isoSio),
.serialOut(serialOut),
.comClk(comClk)
.comClk(cardIsoClk)
);
 
reg sendAtr;
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
reg [7:0] buffer[256+5:0];
localparam CLA_I= 8*4;
localparam INS_I= 8*3;
localparam P1_I = 8*2;
localparam P2_I = 8*1;
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
 
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
 
`include "ComDriverTasks.v"
 
assign isoSio = isTx ? serialOut : 1'bz;
 
reg sendAtr;
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
/*T=0 card model
 
ATR:
3B 00
 
Implemented commands:
write buffer:
tpdu: 00 0C 00 00 LC data
sw: 90 00
read buffer:
tpdu: 00 0A 00 00 LE
response: data
sw: 90 00
any other:
sw: 69 86
*/
task sendAckByte;
sendByte(tpduHeader[INS_I+7:INS_I]);
endtask
 
task writeBufferCmd;
integer i;
begin
sendAckByte;
for(i=0;i<tpduHeader[P3_I+7:P3_I];i=i+1) begin
receiveByte(buffer[i]);
end
sendWord(16'h9000);
end
endtask
 
task readBufferCmd;
integer i;
integer le;
begin
sendAckByte;
le=tpduHeader[P3_I+7:P3_I];
if(0==le) le=256;
for(i=0;i<le;i=i+1) begin
sendByte(buffer[i]);
end
sendWord(16'h9000);
end
endtask
 
integer i;
always @(posedge isoClk, negedge isoReset) begin
if(~isoReset) begin
nWeDataIn<=1'b1;
nCsDataOut<=1'b1;
nCsStatusOut<=1'b1;
tsCnt<=9'b0;
sendAtr<=1'b1;
end else if(tsCnt!=9'd400) begin
78,17 → 138,19
tsCnt <= tsCnt + 1'b1;
end else if(sendAtr) begin
sendAtr<=1'b0;
dataIn<=8'h3B;
nWeDataIn<=1'b0;
@(posedge isoClk)
nWeDataIn<=1'b1;
@(posedge isoClk)//should not be needed
wait(txPending==0);
dataIn<=8'h00;
nWeDataIn<=1'b0;
@(posedge isoClk)
nWeDataIn<=1'b1;
sendByte(8'h3B);
sendByte(8'h00);
waitEndOfTx;
end else begin
//get tpdu
for(i=0;i<5;i=i+1)
receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
//dispatch
case(tpduHeader[7+CLA_I:P2_I])
32'h000C0000: writeBufferCmd;
32'h000A0000: readBufferCmd;
default: sendWord(16'h6986);
endcase
end
end
/trunk/sources/Uart.v
1,4 → 1,5
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
19,31 → 20,31
//
//////////////////////////////////////////////////////////////////////////////////
module BasicHalfDuplexUart(
output [7:0] rxData,
output overrunErrorFlag, //new data has been received before dataOut was read
output dataOutReadyFlag, //new data available
output frameErrorFlag, //bad parity or bad stop bits
output txRun, //tx is started
output endOfRx, //one cycle pulse: 1 during last cycle of last stop bit of rx
output rxRun, //rx is definitely started, one of the three flag will be set
output rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
output txFull,
output isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
output wire [7:0] rxData,
output wire overrunErrorFlag, //new data has been received before dataOut was read
output wire dataOutReadyFlag, //new data available
output wire frameErrorFlag, //bad parity or bad stop bits
output wire txRun, //tx is started
output wire endOfRx, //one cycle pulse: 1 during last cycle of last stop bit of rx
output wire rxRun, //rx is definitely started, one of the three flag will be set
output wire rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
output wire txFull,
output wire isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
input serialIn, //signals to merged into a inout signal according to "isTx"
output serialOut,
output comClk,
input wire serialIn, //signals to merged into a inout signal according to "isTx"
output wire serialOut,
output wire comClk,
input [DIVIDER_WIDTH-1:0] clkPerCycle,
input [7:0] txData,
input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input stopBit2,//0: 1 stop bit, 1: 2 stop bits
input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
input startTx,
input ackFlags,
input clk,
input nReset
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
input wire [7:0] txData,
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
input wire startTx,
input wire ackFlags,
input wire clk,
input wire nReset
);
 
//parameters to override
/trunk/sources/Iso7816_3_Master.v
1,4 → 1,5
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
19,27 → 20,27
//
//////////////////////////////////////////////////////////////////////////////////
module Iso7816_3_Master(
input nReset,
input clk,
input [15:0] clkPerCycle,//not supported yet
input startActivation,//Starts activation sequence
input startDeactivation,//Starts deactivation sequence
input [7:0] dataIn,
input nWeDataIn,
input [12:0] cyclePerEtu,
output [7:0] dataOut,
input nCsDataOut,
output [7:0] statusOut,
input nCsStatusOut,
input wire nReset,
input wire clk,
input wire [15:0] clkPerCycle,//not supported yet
input wire startActivation,//Starts activation sequence
input wire startDeactivation,//Starts deactivation sequence
input wire [7:0] dataIn,
input wire nWeDataIn,
input wire [12:0] cyclePerEtu,
output wire [7:0] dataOut,
input wire nCsDataOut,
output wire [7:0] statusOut,
input wire nCsStatusOut,
output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
output useIndirectConvention,
output tsError,//high if TS character is wrong
output tsReceived,
output atrIsEarly,//high if TS received before 400 cycles after reset release
output atrIsLate,//high if TS is still not received after 40000 cycles after reset release
output wire useIndirectConvention,
output wire tsError,//high if TS character is wrong
output wire tsReceived,
output wire atrIsEarly,//high if TS received before 400 cycles after reset release
output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
//ISO7816 signals
inout isoSio,
output isoClk,
inout wire isoSio,
output wire isoClk,
output reg isoReset,
output reg isoVdd
);
47,8 → 48,9
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
 
assign isoSio = isTx ? serialOut : 1'bz;
pullup(isoSio);
wire serialOut;
assign isoSio = isTx ? serialOut : 1'bz;
pullup(isoSio);
wire comClk;
 
HalfDuplexUartIf uart (
/trunk/sources/Counter.v
1,4 → 1,5
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
20,16 → 21,16
//////////////////////////////////////////////////////////////////////////////////
module Counter(
output reg [WIDTH-1:0] counter,
output earlyMatch,
output wire earlyMatch,
output reg match,
output dividedClk,
input [DIVIDER_WIDTH-1:0] divider, // clock divide factor
input [WIDTH-1:0] compare,
input inc,
input clear,
input [WIDTH_INIT-1:0] initVal,
input clk,
input nReset
output wire dividedClk,
input wire [DIVIDER_WIDTH-1:0] divider, // clock divide factor
input wire [WIDTH-1:0] compare,
input wire inc,
input wire clear,
input wire [WIDTH_INIT-1:0] initVal,
input wire clk,
input wire nReset
);
 
//parameters to override
/trunk/sources/RxCoreSelfContained.v
1,4 → 1,5
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
19,23 → 20,23
//
//////////////////////////////////////////////////////////////////////////////////
module RxCoreSelfContained(
output [7:0] dataOut,
output overrunErrorFlag, //new data has been received before dataOut was read
output dataOutReadyFlag, //new data available
output frameErrorFlag, //bad parity or bad stop bits
output endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
output run, //rx is definitely started, one of the three flag will be set
output startBit, //rx is started, but we don't know yet if real rx or just a glitch
input [DIVIDER_WIDTH-1:0] clkPerCycle,
input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input stopBit2,//0: 1 stop bit, 1: 2 stop bits
input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
input ackFlags,
input serialIn,
input comClk,//not used yet
input clk,
input nReset
output wire [7:0] dataOut,
output wire overrunErrorFlag, //new data has been received before dataOut was read
output wire dataOutReadyFlag, //new data available
output wire frameErrorFlag, //bad parity or bad stop bits
output wire endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
output wire run, //rx is definitely started, one of the three flag will be set
output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
input wire ackFlags,
input wire serialIn,
input wire comClk,//not used yet
input wire clk,
input wire nReset
);
 
//parameters to override
55,7 → 56,8
wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare;
wire bitClocksCounterInc;
wire bitClocksCounterClear;
wire bitClocksCounterInitVal;
wire bitClocksCounterInitVal;
wire dividedClk;
Counter #( .DIVIDER_WIDTH(DIVIDER_WIDTH),
.WIDTH(CLOCK_PER_BIT_WIDTH),
.WIDTH_INIT(1))
62,7 → 64,8
bitClocksCounterModule(
.counter(bitClocksCounter),
.earlyMatch(bitClocksCounterEarlyMatch),
.match(bitClocksCounterMatch),
.match(bitClocksCounterMatch),
.dividedClk(dividedClk),
.divider(clkPerCycle),
.compare(bitClocksCounterCompare),
.inc(bitClocksCounterInc),
/trunk/sources/RxCore.v
1,4 → 1,5
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
25,22 → 26,22
output reg frameErrorFlag, //bad parity or bad stop bits
output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
output reg run, //rx is definitely started, one of the three flag will be set
output startBit, //rx is started, but we don't know yet if real rx or just a glitch
input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input stopBit2,//0: 1 stop bit, 1: 2 stop bits
input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
input ackFlags,
input serialIn,
input clk,
input nReset,
output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
input wire ackFlags,
input wire serialIn,
input wire clk,
input wire nReset,
//to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
output reg bitClocksCounterInc,
output reg bitClocksCounterClear,
output bitClocksCounterInitVal,
input bitClocksCounterEarlyMatch,
input bitClocksCounterMatch
output wire bitClocksCounterInitVal,
input wire bitClocksCounterEarlyMatch,
input wire bitClocksCounterMatch
);
 
//parameters to override
/trunk/sources/TxCore.v
1,4 → 1,5
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Sebastien Riou
19,20 → 20,20
//
//////////////////////////////////////////////////////////////////////////////////
module TxCore(
output comClk,
output serialOut,
output run,
output full,
output stopBits, //1 during stop bits
input [7:0] dataIn,
input [DIVIDER_WIDTH-1:0] clkPerCycle,
input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input loadDataIn, //evaluated only when full=0, when full goes to one, dataIn has been read
input stopBit2,//0: 1 stop bit, 1: 2 stop bits
input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input msbFirst, //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
input clk,
input nReset
output wire comClk,
output wire serialOut,
output wire run,
output wire full,
output wire stopBits, //1 during stop bits
input wire [7:0] dataIn,
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input wire loadDataIn, //evaluated only when full=0, when full goes to one, dataIn has been read
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
input wire msbFirst, //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
input wire clk,
input wire nReset
);
 
//parameters to override
/trunk/sources/HalfDuplexUartIf.v
1,4 → 1,5
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
19,18 → 20,18
//
//////////////////////////////////////////////////////////////////////////////////
module HalfDuplexUartIf(
input nReset,
input clk,
input [DIVIDER_WIDTH-1:0] clkPerCycle,
input [7:0] dataIn,
input nWeDataIn,
output [7:0] dataOut,
input nCsDataOut,
output [7:0] statusOut,
input nCsStatusOut,
input serialIn,
output serialOut,
output comClk
input wire nReset,
input wire clk,
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
input wire [7:0] dataIn,
input wire nWeDataIn,
output wire [7:0] dataOut,
input wire nCsDataOut,
output wire [7:0] statusOut,
input wire nCsStatusOut,
input wire serialIn,
output wire serialOut,
output wire comClk
);
//parameters to override
parameter DIVIDER_WIDTH = 1;

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