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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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  • This comparison shows the changes necessary to convert path 
    /iso7816_3_master
    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/trunk/test/tbIso7816_3_Master.v
32,7 → 32,7
reg startDeactivation;
reg [7:0] dataIn;
reg nWeDataIn;
reg [12:0] cyclePerEtu;
reg [12:0] cyclesPerEtu;
reg nCsDataOut;
reg nCsStatusOut;
 
75,6 → 75,7
wire spy_useT0,spy_useT1,spy_useT15,spy_waitCardTx,spy_waitTermTx,spy_cardTx,spy_termTx,spy_guardTime;
wire spy_overrunError,spy_frameError;
wire [7:0] spy_lastByte;
wire [31:0] spy_bytesCnt;
 
// Instantiate the Unit Under Test (UUT)
Iso7816_3_Master uut (
85,7 → 86,7
.startDeactivation(startDeactivation),
.dataIn(dataIn),
.nWeDataIn(nWeDataIn),
.cyclePerEtu(cyclePerEtu),
.cyclesPerEtu(cyclesPerEtu),
.dataOut(dataOut),
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
142,7 → 143,8
.guardTime(spy_guardTime),
.overrunError(spy_overrunError),
.frameError(spy_frameError),
.lastByte(spy_lastByte)
.lastByte(spy_lastByte),
.bytesCnt(spy_bytesCnt)
);
 
157,7 → 159,7
startDeactivation = 0;
dataIn = 0;
nWeDataIn = 1'b1;
cyclePerEtu = 0;
cyclesPerEtu = 372-1;
nCsDataOut = 1'b1;
nCsStatusOut = 1'b1;
 
206,7 → 208,7
end
initial begin
// timeout
#100000;
#10000000;
tbErrorCnt=tbErrorCnt+1;
$display("ERROR: timeout expired");
#10;
/trunk/test/DummyCard.v
40,7 → 40,7
wire [7:0] dataOut;
wire [7:0] statusOut;
wire serialOut;
reg [12:0] cyclesPerEtu;
 
wire cardIsoClk;//card use its own generated clock (like true UARTs)
HalfDuplexUartIf uartIf (
49,6 → 49,7
.clkPerCycle(clkPerCycle),
.dataIn(dataIn),
.nWeDataIn(nWeDataIn),
.clocksPerBit(cyclesPerEtu),
.dataOut(dataOut),
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
134,6 → 135,7
nCsStatusOut<=1'b1;
tsCnt<=9'b0;
sendAtr<=1'b1;
cyclesPerEtu <= 13'd372-1'b1;
end else if(tsCnt!=9'd400) begin
tsCnt <= tsCnt + 1'b1;
end else if(sendAtr) begin
/trunk/test/iso7816_3_t0_analyzer.v
34,7 → 34,8
output wire guardTime,
output wire overrunError,
output wire frameError,
output reg [7:0] lastByte
output reg [7:0] lastByte,
output reg [31:0] bytesCnt
);
parameter DIVIDER_WIDTH = 1;
48,11 → 49,10
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
//wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
wire txPending=1'b0;
wire txRun=1'b0;
//wire COM_clk=isoClk;
//integer COM_errorCnt;
//wire txPending=1'b0;
//wire txRun=1'b0;
 
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
assign overrunErrorFlag = overrunError;
59,7 → 59,7
assign frameErrorFlag = frameError;
 
wire [7:0] rxData;
reg nCsDataOut;
reg ackFlags;
 
wire msbFirst = useIndirectConvention;
wire sioHighValue = ~useIndirectConvention;
68,7 → 68,7
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
 
 
`include "ComRxDriverTasks.v"
//`include "ComRxDriverTasks.v"
 
wire endOfRx;
 
76,7 → 76,8
 
RxCoreSelfContained #(
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(4'd13))
.CLOCK_PER_BIT_WIDTH(4'd13),
.PRECISE_STOP_BIT(1'b1))
rxCore (
.dataOut(rxData),
.overrunErrorFlag(overrunError),
87,11 → 88,11
.startBit(rxStartBit),
.stopBit(guardTime),
.clkPerCycle(clkPerCycle),
.clocksPerBit(cyclesPerEtu),
.clocksPerBit(cyclesPerEtu-1),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
.ackFlags(nCsDataOut),
.ackFlags(ackFlags),
.serialIn(isoSio),
.comClk(isoClk),
.clk(clk),
140,10 → 141,22
 
wire [1:0] nIfBytes;
HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
reg [7:0] bytesCnt;
 
reg [7:0] tempBytesCnt;
always @(posedge isoClk, negedge nReset) begin
if(~nReset) begin
lastByte<=8'b0;
ackFlags<=1'b0;
bytesCnt<=32'b0;
end else if(ackFlags) begin
ackFlags<=1'b0;
end else if(frameErrorFlag|bufferFull) begin
lastByte<=dataOut;
ackFlags<=1'b1;
bytesCnt<=bytesCnt+1'b1;
end
end
always @(posedge isoClk, negedge nReset) begin
if(~nReset) begin
fiCode<=4'b0001;
diCode<=4'b0001;
useT0<=1'b1;
151,10 → 164,9
useT15<=1'b0;
waitCardTx<=1'b0;
waitTermTx<=1'b0;
lastByte<=8'b0;
fsmState<=ATR_TDI;
atrHasTck<=1'b0;
bytesCnt<=8'h0;
tempBytesCnt<=8'h0;
tdiStruct<=12'h0;
atrCompleted<=1'b0;
end else if(isActivated) begin
165,8 → 177,8
case(fsmState)
ATR_TDI: begin
if(endOfRx) begin
if(bytesCnt==nIfBytes) begin //TDi bytes
bytesCnt <= 2'h0;
if(tempBytesCnt==nIfBytes) begin //TDi bytes
tempBytesCnt <= 2'h0;
tdiStruct <= {tdiCnt+1,dataOut};
if(4'h0==tdiCnt) begin//this is T0
atrK <= dataOut[3:0];
178,17 → 190,17
end
end else begin //TA, TB or TC bytes
//TODO: get relevant info
bytesCnt <= bytesCnt+1;
tempBytesCnt <= tempBytesCnt+1;
end
end
end
ATR_HISTORICAL: begin
if(endOfRx) begin
if(bytesCnt==atrK) begin
if(tempBytesCnt==atrK) begin
atrCompleted <= ~atrHasTck;
fsmState <= atrHasTck ? ATR_TCK : T0_HEADER;
end else begin
bytesCnt <= bytesCnt+1;
tempBytesCnt <= tempBytesCnt+1;
end
end
end
/trunk/sources/Uart.v
97,7 → 97,9
wire stopBit;
// Instantiate the module
RxCoreSelfContained #(
.DIVIDER_WIDTH(DIVIDER_WIDTH))
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
)
rxCore (
.dataOut(rxData),
.overrunErrorFlag(overrunErrorFlag),
118,7 → 120,9
.clk(clk),
.nReset(nReset)
);
TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
)
txCore (
.serialOut(serialOut),
.run(txRun),
/trunk/sources/Iso7816_3_Master.v
27,7 → 27,7
input wire startDeactivation,//Starts deactivation sequence
input wire [7:0] dataIn,
input wire nWeDataIn,
input wire [12:0] cyclePerEtu,
input wire [12:0] cyclesPerEtu,
output wire [7:0] dataOut,
input wire nCsDataOut,
output wire [7:0] statusOut,
53,12 → 53,17
pullup(isoSio);
wire comClk;
 
HalfDuplexUartIf uart (
HalfDuplexUartIf #(
.DIVIDER_WIDTH(1'b1),
.CLOCK_PER_BIT_WIDTH(4'd13)
)
uart (
.nReset(nReset),
.clk(clk),
.clkPerCycle(1'b0),
.dataIn(dataIn),
.nWeDataIn(nWeDataIn),
.clocksPerBit(cyclesPerEtu),
.dataOut(dataOut),
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
/trunk/sources/RxCoreSelfContained.v
42,7 → 42,8
 
//parameters to override
parameter DIVIDER_WIDTH = 1;
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
//invert the polarity of the output or not
//parameter IN_POLARITY = 1'b0;
//parameter PARITY_POLARITY = 1'b1;
60,7 → 61,7
wire bitClocksCounterInitVal;
wire dividedClk;
Counter #( .DIVIDER_WIDTH(DIVIDER_WIDTH),
.WIDTH(CLOCK_PER_BIT_WIDTH),
.WIDTH(CLOCK_PER_BIT_WIDTH),
.WIDTH_INIT(1))
bitClocksCounterModule(
.counter(bitClocksCounter),
75,7 → 76,10
.clk(clk),
.nReset(nReset));
 
RxCore rxCore (
RxCore #( .CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
.PRECISE_STOP_BIT(PRECISE_STOP_BIT)
)
rxCore (
.dataOut(dataOut),
.overrunErrorFlag(overrunErrorFlag),
.dataOutReadyFlag(dataOutReadyFlag),
97,7 → 101,8
.bitClocksCounterCompare(bitClocksCounterCompare),
.bitClocksCounterInc(bitClocksCounterInc),
.bitClocksCounterClear(bitClocksCounterClear),
.bitClocksCounterInitVal(bitClocksCounterInitVal)
.bitClocksCounterInitVal(bitClocksCounterInitVal),
.bitClocksCounter(bitClocksCounter)
);
 
endmodule
/trunk/sources/RxCore.v
27,7 → 27,7
output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
output reg run, //rx is definitely started, one of the three flag will be set
output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
output wire stopBit, //rx is over but still in stop bits
output reg stopBit, //rx is over but still in stop bits
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
42,11 → 42,13
output reg bitClocksCounterClear,
output wire bitClocksCounterInitVal,
input wire bitClocksCounterEarlyMatch,
input wire bitClocksCounterMatch
input wire bitClocksCounterMatch,
input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter
);
 
//parameters to override
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
 
//default conventions
parameter START_BIT = 1'b0;
75,7 → 77,7
wire parityError;
 
assign startBit = (nextState == START_STATE);
assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
//assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
assign internalIn = serialIn;
assign parityError= parityBit ^ internalIn ^ 1'b1;
reg flagsSet;
117,14 → 119,17
dataOutReadyFlag <= #1 0;
frameErrorFlag <= #1 0;
run <= #1 0;
endOfRx <= #1 0;
endOfRx <= #1 0;
stopBit<= #1 0;
end else begin
case(nextState)
IDLE_STATE: begin
if(bitClocksCounterEarlyMatch)
endOfRx <= #1 1'b1;
if(bitClocksCounterMatch)
endOfRx <= #1 0;
if(bitClocksCounterMatch) begin
endOfRx <= #1 0;
stopBit <= #1 0;
end
if(ackFlags) begin
//overrunErrorFlag is auto cleared at PARITY_STATE
//meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
188,7 → 193,8
end else if(ackFlags) begin
frameErrorFlag <= #1 0;
end
flagsSet=1;
flagsSet=1;
if(PRECISE_STOP_BIT==0) stopBit <= #1 1;
if(stopBit2)
nextState <= #1 STOP1_STATE;
else
211,6 → 217,11
nextState <= #1 STOP2_STATE;
end else if(ackFlags) begin
frameErrorFlag <= #1 0;
end
if(PRECISE_STOP_BIT!=0) begin
if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
stopBit <= #1 1;
end
end
end
STOP2_STATE: begin
226,6 → 237,11
nextState <= #1 IDLE_STATE;
end else if(ackFlags) begin
frameErrorFlag <= #1 0;
end
if(PRECISE_STOP_BIT!=0) begin
if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
stopBit <= #1 1;
end
end
end
default: nextState <= #1 IDLE_STATE;
/trunk/sources/HalfDuplexUartIf.v
25,6 → 25,7
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
input wire [7:0] dataIn,
input wire nWeDataIn,
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
output wire [7:0] dataOut,
input wire nCsDataOut,
output wire [7:0] statusOut,
34,13 → 35,14
output wire comClk
);
//parameters to override
parameter DIVIDER_WIDTH = 1;
parameter DIVIDER_WIDTH = 1;
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
 
reg [7:0] dataReg;
 
// Inputs
wire [7:0] txData;
wire [12:0] clocksPerBit;
//wire [12:0] clocksPerBit;
wire stopBit2=1;
wire oddParity=0; //if 1, parity bit is such that data+parity have an odd number of 1
wire msbFirst=0; //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
64,7 → 66,7
reg [1:0] flagsReg;
assign txData = dataReg;
assign clocksPerBit = 7;
//assign clocksPerBit = 7;
 
assign dataOut=dataReg;
assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
105,7 → 107,10
end
end
 
BasicHalfDuplexUart #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
BasicHalfDuplexUart #(
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
)
uart (
.rxData(rxData),
.overrunErrorFlag(overrunErrorFlag),

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