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https://opencores.org/ocsvn/jart/jart/trunk
Subversion Repositories jart
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/jart/branches/ver0branch
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/zu.vhd
0,0 → 1,63
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_signed.all; |
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entity zu is |
generic |
( |
VALSTART : integer := 2 |
); |
port ( |
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clk, rst, ena : in std_logic; -- The usual control signals |
clr : in std_logic; |
zpos : out integer range 0 to 1023 |
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); |
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end entity; |
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architecture rtl of zu is |
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begin |
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process (clk,rst,ena,clr) |
variable pivot : integer range 0 to 15; |
variable z : integer range 0 to 1023; |
begin |
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if rst='0' then |
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zpos<=VALSTART; |
z:=VALSTART; |
pivot:=1; |
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elsif rising_edge(clk) and ena='1' then |
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if clr='1' then |
z:=VALSTART; |
pivot:=0; |
elsif pivot=4 then |
z:=z+2; |
elsif pivot=9 then |
z:=z+1; |
else |
z:=z+3; |
end if; |
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if pivot = 9 then |
pivot := 0; |
else |
pivot:=pivot+1; |
end if; |
zpos <= z; |
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end if; |
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end process; |
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end rtl; |
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